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features ? 1066 mhz ddr operation (2133 mb/s/ball data rate) ? 76.8 gb/s peak bandwidth (x36 at 1066 mhz clock frequency) ? organization ? 32 meg x 18, and 16 meg x 36 common i/o (cio) ? 16 banks ? 1.2v center-terminated push/pull i/o ? 2.5v v ext , 1.35v v dd , 1.2v v ddq i/o ? reduced cy cle time ( t rc (min) = 8 - 12ns) ? sdr addressing ? programmable read/write latency (rl/wl) and burst length ? data mask for write commands ? differential input clocks (ck, ck#) ? free-running differential input data clocks (dkx, dkx#) and output data clocks (qkx, qkx#) ? on-die dll generates ck edge-aligned data and differential output data clock signals ? 64ms refresh (128k refresh per 64ms) ? 168-ball fbga package ? 40 or 60 matched impedance outputs ? integrated on-die termination (odt) ? single or multibank writes ? extended operating range (200?1066 mhz) ? read training register ? multiplexed and non-multiplexed addressing capa- bilities ? mirror function ? output driver and odt calibration ? jtag interface (ieee 1149.1-2001) options ? clock cycle and t rc timing ? 0.93ns and t rc (min) = 8ns (rl3-2133) ? 0.93ns and t rc (min) = 10ns (rl3-2133) ? 1.07ns and t rc (min) = 8ns (rl3-1866) ? 1.07ns and t rc (min) = 10ns (rl3-1866) ? 1.25ns and t rc (min) = 10ns (rl3-1600) ? 1.25ns and t rc (min) = 12ns (rl3-1600) ? configuration ? 32 meg x 18 ? 16 meg x 36 ? operating temperature ? commercial (t c = 0 to +95c) ? industrial (t c = ?40c to +95c) ? package ? 168-ball fbga ? 168-ball fbga (pb-free) ? revision 576mb: x18, x36 rldram 3 features rldram 3 is49rl18320 ? 2 meg x 18 x 16 banks IS49RL36160 ? 1 meg x 36 x 16 banks copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances integrated silicon solution, inc. ? www.issi.com 01/17/2012 1
figure 1: 576mb rldram ? 3 part numbers package 168-ball fbga 168-ball fbga (lead-free) example part number: is49rl18320-093ebl t ck = 0.93ns (8ns t rc) t ck = 0.93ns (10ns t rc) t ck = 1.07ns (8ns t rc) t ck = 1.07ns (10ns t rc) t ck = 1.25ns (10ns t rc) t ck = 1.25ns (12ns t rc) speed grade -093e -093 -107e -107 -125e -125 - configuration is49rl package speed temp temperature commercial industrial none i configuration 32 meg x 18 16 meg x 36 18320 36160 b bl bga part marking decoder due to space limitations, bga-packaged components have an abbreviated part marking that is different from the part number. issi?s bga part marking decoder is available on issi?s web site at www.issi.com 576mb: x18, x36 rldram3 features integrated silicon solution, inc. ? www.issi.com 01/17/2012 2
contents general descr iption ......................................................................................................................................... 8 g eneral notes .............................................................................................................................................. 8 state diagram .................................................................................................................................................. 9 functional block diagrams ............................................................................................................................. 10 ball assignments and descriptions ................................................................................................................. 12 package dimensions ....................................................................................................................................... 16 electrical characteristics C i dd specifications .................................................................................................. 17 electrical specifications C absolute ratings and i/o capacitance ..................................................................... 21 absolute maximum ratings ........................................................................................................................ 21 input/output capacitance .......................................................................................................................... 21 ac and dc operating conditions .................................................................................................................... 22 ac overshoot/undershoot specifications .................................................................................................... 24 slew rate definitions for single-ended input signals ................................................................................... 27 slew rate definitions for differential input signals ...................................................................................... 29 odt characteristics ....................................................................................................................................... 30 odt resistors ............................................................................................................................................ 30 odt sensitivity .......................................................................................................................................... 32 output driver impedance ............................................................................................................................... 33 output driver sensitivity ............................................................................................................................ 35 output characteristics and operating conditions ............................................................................................ 36 reference output load ............................................................................................................................... 39 slew rate definitions for single-ended output signals ..................................................................................... 40 slew rate definitions for differential output signals ........................................................................................ 41 speed bin tables ............................................................................................................................................ 42 ac electrical characteristics ........................................................................................................................... 43 temperature and thermal impedance characteristics ..................................................................................... 48 command and address setup, hold, and derating ........................................................................................... 50 data setup, hold, and derating ....................................................................................................................... 56 commands .................................................................................................................................................... 62 mode register set (mrs) command ......................................................................................................... 63 mode register 0 (mr0) .................................................................................................................................... 64 t rc ............................................................................................................................................................. 65 data latency .............................................................................................................................................. 65 dll enable/disable ................................................................................................................................... 65 address multiplexing .................................................................................................................................. 65 mode register 1 (mr1) .................................................................................................................................... 67 output drive impedance ............................................................................................................................ 67 dq on-die termination (odt) ................................................................................................................... 67 dll reset ................................................................................................................................................... 67 zq calibration ............................................................................................................................................ 68 zq calibration long ................................................................................................................................... 69 zq calibration short ................................................................................................................................... 69 auto refresh protocol ............................................................................................................................ 70 burst length (bl) ....................................................................................................................................... 70 mode register 2 (mr2) .................................................................................................................................... 72 read training register (rtr) ..................................................................................................................... 72 write protocol .......................................................................................................................................... 74 write command .......................................................................................................................................... 74 multibank write ....................................................................................................................................... 75 read command ............................................................................................................................................ 75 576mb: x18, x36 rldram 3 features integrated silicon solution, inc. ? www.issi.com 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auto refresh command ............................................................................................................................ 77 initialization operation ............................................................................................................................ 79 write operation ........................................................................................................................................... 82 read operation ............................................................................................................................................. 86 auto refresh operation ............................................................................................................................. 89 multiplexed address mode .............................................................................................................................. 92 data latency in multiplexed address mode ................................................................................................. 97 refresh command in multiplexed address mode ..................................................................................... 97 mirror function ............................................................................................................................................ 101 reset operation ........................................................................................................................................... 101 ieee 1149.1 serial boundary scan (jtag) ....................................................................................................... 102 disabling the jtag feature ........................................................................................................................ 102 test access port (tap) ................................................................................................................................ 102 tap controller ........................................................................................................................................... 103 performing a tap reset ............................................................................................................................ 105 tap registers ............................................................................................................................................ 105 tap instruction set .................................................................................................................................... 106 revision history ............................................................................................................................................ 113 rev. b, advance ? 10/11 .............................................................................................................................. 113 rev. a, advance ? 6/11 ............................................................................................................................... 113 576mb: x18, x36 rldram 3 features integrated silicon solution, inc. ? www.issi.com 01/17/2012 4
list of figures figure 1: 576mb rldram ? 3 par t n umbers ..................................................................................................... 2 figure 2: simplified state diagram ................................................................................................................... 9 figure 3: 32 meg x 18 functional block diagram ............................................................................................. 10 figure 4: 16 meg x 36 functional block diagram ............................................................................................. 11 figure 5: 168-ball fbga ................................................................................................................................. 16 figure 6: single-ended input signal ............................................................................................................... 23 figure 7: overshoot ....................................................................................................................................... 24 figure 8: undershoot .................................................................................................................................... 24 figure 9: v ix for differential signals ................................................................................................................ 25 figure 10: single-ended requirements for differential signals ........................................................................ 26 figure 11: definition of differential ac swing and t dvac ................................................................................ 26 figure 12: nominal slew rate definition for single-ended input signals .......................................................... 28 figure 13: nominal differential input slew rate definition for ck, ck#, dk x, and dkx# .................................. 29 figure 14: odt levels and i-v characteristics ................................................................................................ 30 figure 15: output driver ................................................................................................................................ 33 figure 16: dq output signal .......................................................................................................................... 38 figure 17: differential output signal .............................................................................................................. 39 figure 18: reference output load for ac timing and output slew rate ........................................................... 39 figure 19: nominal slew rate definition for single-ended output signals ....................................................... 40 figure 20: nominal differential output slew rate definition for qkx, qkx# ..................................................... 41 figure 21: example temperature test point location ...................................................................................... 49 figure 22: nominal slew rate and t vac for t is (command and address - clock) ............................................... 52 figure 23: nominal slew rate for t ih (command and address - clock) ............................................................ 53 figure 24: tangent line for t is (command and address - clock) ...................................................................... 54 figure 25: tangent line for t ih (command and address - clock) ..................................................................... 55 figure 26: nominal slew rate and t vac for t ds (dq - strobe) .......................................................................... 58 figure 27: nominal slew rate for t dh (dq - strobe) ........................................................................................ 59 figure 28: tangent line for t ds (dq - strobe) ................................................................................................. 60 figure 29: tangent line for t dh (dq - strobe) ................................................................................................ 61 figure 30: mrs command protocol ............................................................................................................... 63 figure 31: mr0 definition for non-multiplexed address mode ........................................................................ 64 figure 32: mr1 definition for non-multiplexed address mode ........................................................................ 67 figure 33: zq calibration timing (zqcl and zqcs) ....................................................................................... 69 figure 34: read burst lengths ........................................................................................................................ 71 figure 35: mr2 definition for non-multiplexed address mode ........................................................................ 72 figure 36: read training function - back-to-back readout ............................................................................ 73 figure 37: write command ......................................................................................................................... 74 figure 38: read command ........................................................................................................................... 76 figure 39: bank address-controlled auto refresh command ..................................................................... 77 figure 40: multibank auto refresh command ........................................................................................... 78 figure 41: power-up/initialization sequence ................................................................................................. 80 figure 42: write burst ................................................................................................................................. 82 figure 43: consecutive write bursts ............................................................................................................. 83 figure 44: write-to-read ............................................................................................................................ 83 figure 45: write - dm operation .................................................................................................................. 84 figure 46: consecutive quad bank write bursts ........................................................................................... 85 figure 47: interleaved read and quad bank write bursts ............................................................................. 85 figure 48: basic read burst .......................................................................................................................... 86 figure 49: consecutive read bursts (bl = 2) .................................................................................................. 87 figure 50: consecutive read bursts (bl = 4) .................................................................................................. 87 576mb: x18, x36 rldram 3 features integrated silicon solution, inc. ? www.issi.com 01/17/2012 5
figure 51: read-to-write ............................................................................................................................ 88 figure 52: read d ata valid window ................................................................................................................ 88 figure 53: bank address-controlled auto refresh cycle ............................................................................. 89 figure 54: multibank auto refresh cycle ................................................................................................... 89 figure 55: read burst with odt .................................................................................................................... 90 figure 56: read-nop-read with odt .......................................................................................................... 91 figure 57: command description in multiplexed address mode ..................................................................... 92 figure 58: power-up/initialization sequence in multiplexed address mode ..................................................... 93 figure 59: mr0 definition for multiplexed address mode ................................................................................ 94 figure 60: mr1 definition for multiplexed address mode ................................................................................ 95 figure 61: mr2 definition for multiplexed address mode ................................................................................ 96 figure 62: bank address-controlled auto refresh operation with multiplexed addressing .......................... 97 figure 63: multibank auto refresh operation with multiplexed addressing ................................................ 97 figure 64: consecutive write bursts with multiplexed addressing ................................................................. 98 figure 65: write-to-read with multiplexed addressing ................................................................................ 99 figure 66: consecutive read bursts with multiplexed addressing ................................................................... 99 figure 67: read-to-write with multiplexed addressing ............................................................................... 100 figure 68: tap controller state diagram ........................................................................................................ 104 figure 69: tap controller functional block diagram ..................................................................................... 104 figure 70: jtag operation - loading instruction code and shifting out data ................................................. 107 figure 71: tap timing .................................................................................................................................. 108 576mb: x18, x36 rldram 3 featur es integrated silicon solution, inc. ? www.issi.com 01/17/2012 6
list of tables table 1: 32 meg x 18 b all assignments ? 168-b all fbga (top view) .................................................................. 12 table 2: 16 meg x 36 ball assignments ? 168-ball fbga (top view) .................................................................. 13 table 3: ball descriptions .............................................................................................................................. 14 table 4: i dd operating conditions and maximum limits ................................................................................ 17 table 5: absolute maximum ratings .............................................................................................................. 21 table 6: input/output capacitance ................................................................................................................ 21 table 7: dc electrical characteristics and operating conditions ..................................................................... 22 table 8: input ac logic levels ........................................................................................................................ 22 table 9: control and address balls ................................................................................................................. 24 table 10: clock, data, strobe, and mask balls ................................................................................................. 24 table 11: differential input operating conditions (ck, ck# and dkx, dkx#) ................................................... 25 table 12: allowed time before ringback ( t dvac) for ck, ck#, dkx, and dk x# ................................................. 27 table 13: single-ended input slew rate definition .......................................................................................... 27 table 14: differential input slew rate definition ............................................................................................. 29 table 15: odt dc electrical characteristics ................................................................................................... 30 table 16: r tt effective impedances ................................................................................................................ 31 table 17: odt sensitivity definition .............................................................................................................. 32 table 18: odt temperature and voltage sensitivity ........................................................................................ 32 table 19: driver pull-up and pull-down impedance calculations ................................................................... 34 table 20: output driver sensitivity definition ................................................................................................. 35 table 21: output driver voltage and temperature sensitivity .......................................................................... 35 table 22: single-ended output driver characteristics ..................................................................................... 36 table 23: differential output driver characteristics ........................................................................................ 37 table 24: single-ended output slew rate definition ....................................................................................... 40 table 25: differential output slew rate definition .......................................................................................... 41 table 26: rl3 speed bins ............................................................................................................................... 42 table 27: ac electrical characteristics ............................................................................................................ 43 table 28: temperature limits ......................................................................................................................... 48 table 29: thermal impedance ........................................................................................................................ 48 table 30: command and address setup and hold values referenced at 1 v/ns ? ac/dc-based ........................ 50 table 31: derating values for t is/ t ih ? ac150/dc100-based ............................................................................ 51 table 32: minimum required time t vac above v ih(ac) (or below v il(ac) ) for valid transition ............................ 51 table 33: data setup and hold values at 1 v/ns (dkx, dkx# at 2v/ns) ? ac/dc-based ..................................... 56 table 34: derating values for t ds/ t dh ? ac150/dc100-based ......................................................................... 57 table 35: minimum required time t vac above v ih(ac) (or below v il(ac) ) for valid transition ............................ 57 table 36: command descriptions .................................................................................................................. 62 table 37: command table ............................................................................................................................. 62 table 38: trc_mrs mr0[3:0] values ............................................................................................................... 65 table 39: address widths of different burst lengths ....................................................................................... 70 table 40: address mapping in multiplexed address mode ............................................................................... 96 table 41: 32 meg x 18 ball assignments with mf ball tied high ..................................................................... 101 table 42: tap input ac logic levels .............................................................................................................. 108 table 43: tap ac electrical characteristics .................................................................................................... 108 table 44: tap dc electrical characteristics and operating conditions ............................................................ 109 table 45: identification register definitions .................................................................................................. 109 table 46: scan register sizes ......................................................................................................................... 110 table 47: instruction codes .......................................................................................................................... 110 table 48: boundary scan (exit) ..................................................................................................................... 110 table 49: ordering information ..................................................................................................................... 112 576mb: x18, x36 rldram 3 features integrated silicon solution, inc. ? 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general description the issi rldram ? 3 is a high-speed memory device designed for high-bandwidth data storage?telecommunications, networking, cache applications, etc. the chip?s 16- bank architecture is optimized for sustainable high-speed operation. the ddr i/o interface transfers two data bits per clock cycle at the i/o balls. output data is referenced to the read strobes. commands, addresses, and control signals are also registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data strobes. read and write accesses to the rl3 device are burst-oriented. the burst length (bl) is programmable to 2, 4, or 8 by a setting in the mode register. the device is supplied with 1.35v for the core and 1.2v for the output drivers. the 2.5v supply is used for an internal supply. bank-scheduled refresh is supported with the row address generated internally. the 168-ball fbga package is used to enable ultra-high-speed data transfer rates. general notes ? the functionality and the timing specifications discussed in this data sheet are for the dll enable mode of operation. ? any functionality not specifically stated is considered undefined, illegal, and not sup- ported, and can result in unknown operation. ? nominal conditions are assumed for specifications not defined within the figures shown in this data sheet. ? throughout this data sheet, the terms "rldram," "dram,? and "rldram 3" are all used interchangeably and refer to the rldram 3 sdram device. ? references to dq, dk, qk, dm, and qvld are to be interpeted as each group collec- tively, unless specifically stated otherwise. this includes true and complement signals of differential signals. ? non-multiplexed operation is assumed if not specified as multiplexed. 576mb: x18, x36 rldram 3 general description integrated silicon solution, inc. ? www.issi.com 01/17/2012 8
state diagram figure 2: simplified state diagram initialization sequence nop read write reset# mrs aref automatic sequence command sequence 576mb: x18, x36 rldram 3 state diagram integrated silicon solution, inc. ? www.issi.com 01/17/2012 9
functional block diagrams figure 3: 32 meg x 18 functional block diagram 13 ck# cs# ck 8 a[19:0] 1 ba[3:0] zq zqcl, zqcs rzq ref# we# mf tck tms tdi reset# 24 32 i/o gating dqm mask logic column decoder bank 0 memory array (8192 x 32 x 8 x 18) 2 8192 bank control logic bank 1 bank 0 bank 14 bank 15 13 7 1 4 16 16 refresh counter 13 24 mode register command decode control logic row- address mux address register jtag logic and boundary scan register column- address counter/ latch 7 1 144 read logic write fifo and drivers clk in 144 144 n n 18 18 18 4 18 4 2 dq latch qk/qk# generator read drivers dll ck/ck# rcvrs input logic (0 ....17) (0...3) v ddq/2 r tt v ddq/2 r tt odt control odt control r tt odt control odt control dq[17:0] qvld tdo qk0/qk0#,qk1/qk1# dk0/dk0#, dk1/dk1# dm[1:0] zq cal zq cal zq cal 5 2 1 2 1 sense amplifiers sense amplifiers 8192 18 18 bank 0 row- address latch and decoder v ddq/2 notes: 1. example for bl = 2; column address will be reduced with an increase in burst length. 2. 8 = (length of burst) x 2^ (number of column addresses to write fifo and read logic). draft 12/19/2011 576mb: x18, x36 rldram 3 functional block diagrams integrated silicon solution, inc. ? www.issi.com 01/17/2012 10
functional block diagrams figure 4: 16 meg x 36 functional block diagram 13 ck# cs# ck 8 a[18:0] 1 tck tms tdi zq zqcl, zqcs rzq ref# we# mf reset# 23 32 i/o gating dqm mask logic column decoder bank 0 memory array (8192 x 32 x 4 x 36) 2 8192 bank control logic bank 1 bank 0 bank 14 bank 15 13 6 1 4 16 16 refresh counter 13 23 mode register command decode control logic row- address mux address register jtag logic and boundary scan register column- address counter/ latch 6 1 144 read logic write fifo and drivers clk in 144 144 n n 36 36 36 8 4 2 36 dq latch qk/qk# generator read drivers dll ck/ck# rcvrs input logic (0 ....35) (0...3) vddq/2 v ddq/2 r tt r tt vddq/2 odt control odt control odt control odt control r tt dq[35:0] qk0/qk0#, qk1/qk1# qk2/qk2#, qk3/qk3# qvld[1:0] dk0/dk0#, dk1/dk1# dm[1:0] tdo zq cal zq cal zq cal 5 1 1 1 1 sense amplifiers sense amplifiers 8192 36 36 bank 0 row- address latch and decoder notes: 1. example for bl = 2; column address will be reduced with an increase in burst length. 2. 4 = (length of burst) x 2^ (number of column addresses to write fifo and read logic). draft 12/19/2011 576mb: x18, x36 rldram 3 functional block diagrams integrated silicon solution, inc. ? www.issi.com 01/17/2012 11
ball assignments and descriptions table 1: 32 meg x 18 ball assignments C 168-ball fbga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 a v ss v dd nf v ddq nf v ref dq7 v ddq dq8 v dd v ss reset# b v ext v ss nf v ssq nf v ddq dm0 v ddq dq5 v ssq dq6 v ss v ext c v dd nf v ddq nf v ssq nf dk0# dq2 v ssq dq3 v ddq dq4 v dd d a11 v ssq nf v ddq nf v ssq dk0 v ssq qk0 v ddq dq0 v ssq a13 e v ss a0 v ssq nf v ddq nf mf qk0# v ddq dq1 v ssq cs# v ss f a7 nf (a20) 1 v dd a2 a1 we# zq ref# a3 a4 v dd a5 a9 g v ss a15 a6 v ss ba1 v ss ck# v ss ba0 v ss a8 a18 v ss h a19 v dd a14 a16 v dd ba3 ck ba2 v dd a17 a12 v dd a10 j v ddq nf v ssq nf v ddq nf v ss qk1# v ddq dq9 v ssq qvld v ddq k nf v ssq nf v ddq nf v ssq dk1 v ssq qk1 v ddq dq10 v ssq dq11 l v dd nf v ddq nf v ssq nf dk1# dq12 v ssq dq13 v ddq dq14 v dd m v ext v ss nf v ssq nf v ddq dm1 v ddq dq15 v ssq dq16 v ss v ext n v ss tck v dd tdo v ddq nf v ref dq17 v ddq tdi v dd tms v ss notes: 1. location of the additional address signal (a20) required on the 1gb rldram 3 x18 con- figuration. internally connected so it can mirror the a5 address signal when mf is asser - ted high. has parasitic characteristics of an address pin. 2. nf balls for the x18 configuration are internally connected and have parasitic character - istics of an i/o. balls may be connected to v ssq . 3. mf is assumed to be tied low for this ball assignment. 576mb: x18, x36 rldram 3 ball assignments and descriptions integrated silicon solution, inc. ? www.issi.com 01/17/2012 12
table 2: 16 meg x 36 ball assignments C 168-ball fbga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 a v ss v dd dq26 v ddq dq25 v ref dq7 v ddq dq8 v dd v ss reset# b v ext v ss dq24 v ssq dq23 v ddq dm0 v ddq dq5 v ssq dq6 v ss v ext c v dd dq22 v ddq dq21 v ssq dq20 dk0# dq2 v ssq dq3 v ddq dq4 v dd d a11 v ssq dq18 v ddq qk2 v ssq dk0 v ssq qk0 v ddq dq0 v ssq a13 e v ss a0 v ssq dq19 v ddq qk2# mf qk0# v ddq dq1 v ssq cs# v ss f a7 nf (a20) 1 v dd a2 a1 we# zq ref# a3 a4 v dd a5 a9 g v ss a15 a6 v ss ba1 v ss ck# v ss ba0 v ss a8 a18 v ss h nf (a19) 2 v dd a14 a16 v dd ba3 ck ba2 v dd a17 a12 v dd a10 j v ddq qvld1 v ssq dq27 v ddq qk3# v ss qk1# v ddq dq9 v ssq qvld0 v ddq k dq29 v ssq dq28 v ddq qk3 v ssq dk1 v ssq qk1 v ddq dq10 v ssq dq11 l v dd dq32 v ddq dq31 v ssq dq30 dk1# dq12 v ssq dq13 v ddq dq14 v dd m v ext v ss dq34 v ssq dq33 v ddq dm1 v ddq dq15 v ssq dq16 v ss v ext n v ss tck v dd tdo v ddq dq35 v ref dq17 v ddq tdi v dd tms v ss notes: 1. location of the additional address signal (a20) required on the 1gb rldram 3 x18 con- figuration. internally connected so it can mirror the a5 address signal when mf is asser - ted high. has parasitic characteristics of an address pin. 2. nf ball for x36 configuration is internally connected and has parasitic characteristics of an address (a19 for x18 configuration). ball may be connected to v ssq . 3. mf is assumed to be tied low for this ball assignment. 576mb: x18, x36 rldram 3 ball assignments and descriptions integrated silicon solution, inc. ? www.issi.com 01/17/2012 13
table 3: ball descriptions symbol type description a[19:0] input address inputs: a[19:0] define the row and column addresses for read and write operations. during a mode register set , the address inputs define the register settings along with ba[3:0]. they are sampled at the rising edge of ck. ba[3:0] input bank addr ess inputs: select the internal bank to which a command is being applied. ck/ck# input input clock: ck and ck# are differential input clocks. addresses and commands are latched on the rising edge of ck. cs# input chip select: cs# enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands are ignored, but internal operations contin- ue. dq[35:0] i/o data input: the dq signals form the 36-bit data bus. during read commands, the data is refer- enced to both edges of qk. during write commands, the data is sampled at both edges of dk. dkx, dkx # input input data clock: dkx and dkx # are differential input data clocks. all input data is referenced to both edges of dkx. for the x36 device, dq[8:0] and dq[26:18] are referenced to dk0 and dk0#, and dq[17:9] and dq[35:27] are referenced to dk1 and dk1#. for the x18 device, dq[8:0] are referenced to dk0 and dk0#, and dq[17:9] are referenced to dk1 and dk1#. dkx and dkx# are free-running signals and must always be supplied to the device. dm[1:0] input input data mask: dm is the input mask signal for write data. input data is masked when dm is sampled high. dm0 is used to mask the lower byte for the x18 device and dq[8:0] and dq[26:18] for the x36 device. dm1 is used to mask the upper byte for the x18 device and dq[17:9] and dq[35:27] for the x36 device. tie dm[1:0] to v ss if not used. tck input ieee 1149.1 clock input: this ball must be tied to v ss if the jtag function is not used. tms, tdi input ieee 1149.1 test inputs: these balls may be left as no connects if the jtag function is not used. we#, ref# input command inputs: sampled at the positive edge of ck, we# and ref# (together with cs#) de- fine the command to be executed. reset# input reset: reset# is an active low cmos input referenced to v ss . reset# assertion and deassertion are asynchronous. reset# is a cmos input defined with dc high 0.8 x v dd and dc low 0.2 x v ddq . zq input external impedance: this signal is used to tune the devices output impedance and odt. rzq needs to be 240, where rzq is a resistor from this signal to ground. qkx, qkx # output output data clocks: qk and qk# are opposite-polarity output data clocks. they are free-run- ning signals and during read commands are edge-aligned with the dqs. for the x36 device, qk0, qk0# align with dq[8:0]; qk1, qk1# align with dq[17:9]; qk2, qk2# align with dq[26:18]; qk3, qk3# align with dq[35:27]. for the x18 device, qk0, qk0# align with dq[8:0]; qk1, qk1# align with dq[17:9]. qvldx output data valid: the qvld ball indicates that valid output data will be available on the subsequent rising clock edge. there is a single qvld ball for the x18 device and two, qvld0 and qvld1, for the x36 device. qvld0 aligns with dq[17:0]; qvld1 aligns with dq[35:18]. mf input mirror function: the mirror function ball is a dc input used to create mirrored ballouts for sim- ple dual-loaded clamshell mounting. if the ball is tied to v ss , the address and command balls are in their true layout. if the ball is tied to v ddq , they are in the complement location. mf must be tied high or low and cannot be left floating. mf is a cmos input defined with dc high 0.8 x v dd and dc low 0.2 x v ddq . 576mb: x18, x36 rldram 3 ball assignments and descriptions integrated silicon solution, inc. ? www.issi.com 01/17/2012 14
table 3: ball descriptions (continued) symbol type description tdo output ieee 1149.1 test output: jt ag output. this ball may be left as no connect if the jt ag function is not used. v dd supply power supply: 1.35v nominal. see t able 7 (page 22) for range. v ddq supply dq power supply: 1.2v nominal. isolated on the device for improved noise immunity. see t a- ble 7 (page 22) for range. v ext supply power supply: 2.5v nominal. see t able 7 (page 22) for range. v ref supply input reference voltage: v ddq /2 nominal. provides a reference voltage for the input buf fers. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity . nc C no connect: these balls are not connected to the dram. nf C no function: these balls are connected to the dram, but provide no functionality. 576mb: x18, x36 rldram 3 ball assignments and descriptions integrated silicon solution, inc. ? www.issi.com 01/17/2012 15
package dimensions figure 5: 168-ball fbga seating plane 0.12 a 13 ball a1 id ball a1 id a 0.325 min 1.1 0.1 12 ctr 13.5 0.1 1 typ 12 ctr 13.5 0.1 168x ?0.55 dimensions apply to solder balls post- reflow on ?0.40 nsmd ball pads. 1 typ a b c d e f g h j k l m n 12 11 10 9 8 7 6 5 4 3 2 1 note: 1. all dimensions are in millimeters. 576mb: x18, x36 rldram 3 package dimensions integrated silicon solution, inc. ? www.issi.com 01/17/2012 16
electrical characteristics C i dd specifications table 4: i dd operating conditions and maximum limits notes 1C6 apply to the entire table description condition symbol -093e -093 -107e -107 -125e -125 units notes standby current t ck = idle; all banks idle; no inputs toggling i sb1 (v dd ) x18 125 125 125 125 125 125 ma 7 i sb1 (v dd ) x36 125 125 125 125 125 125 i sb1 (v ext ) 30 30 30 30 30 30 clock active standby cur - rent cs# = 1; no commands; bank ad- dress incremented and half ad- dress/data change once every four clock cycles i sb2 (v dd ) x18 870 870 815 815 725 725 ma i sb2 (v dd ) x36 895 895 835 835 740 740 i sb2 (v ext ) 30 30 30 30 30 30 operational current: bl2 bl = 2; sequential bank access; bank transitions once every t rc; half address transitions once every t rc; read followed by write se- quence; continuous data during write commands i dd1 (v dd ) x18 1175 1115 1100 1045 940 915 ma i dd1 (v dd ) x36 1185 1125 1110 1055 950 925 i dd1 (v ext ) 35 35 35 35 35 35 operational current: bl4 bl = 4; sequential bank access; bank transitions once every t rc; half address transitions once every t rc; read followed by write se- quence; continuous data during write commands i dd2 (v dd ) x18 1205 1145 1130 1075 970 945 ma i dd2 (v dd ) x36 1215 1155 1140 1080 980 950 i dd2 (v ext ) 35 35 35 35 35 35 operational current: bl8 bl = 8; sequential bank access; bank transitions once every t rc; half address transitions once every t rc; read followed by write se- quence; continuous data during write commands i dd3 (v dd ) x18 1300 1220 1200 1130 1030 1000 ma i dd3 (v dd ) x36 na na na na na na i dd3 (v ext ) 35 35 35 35 35 35 burst refresh current sixteen bank cyclic refresh using bank address control aref proto- col; command bus remains in re- fresh for all sixteen banks; dqs are high-z and at v ddq /2; addresses are at v ddq /2 i ref1 (v dd ) x18 1550 1550 1400 1400 1230 1230 ma i ref1 (v dd ) x36 1570 1570 1420 1420 1245 1245 i ref1 (v ext ) 80 80 75 75 70 70 draft 12/19/2011 576mb: x18, x36 rldram 3 electrical characteristics C i dd specifications integrated silicon solution, inc. ? www.issi.com 01/17/2012 17
table 4: i dd operating conditions and maximum limits (continued) notes 1C6 apply to the entire table description condition symbol -093e -093 -107e -107 -125e -125 units notes distributed refresh cur - rent single bank refresh using bank ad- dress control aref protocol; se- quential bank access every 0.489 s; dqs are high-z and at v ddq /2; ad- dresses are at v ddq /2 i ref2 (v dd ) x18 855 855 800 800 710 710 ma i ref2 (v dd ) x36 875 875 815 815 725 725 i ref2 (v ext ) 30 30 30 30 30 30 multibank re- fresh current: 4 bank re- fresh quad bank refresh using multi- bank aref protocol; bl=4; cyclic bank access; subject to t saw and t mmd specifications; dqs are high- z and at v ddq /2; bank addresses are at v ddq /2 i mbref4 (v dd ) x18 1965 1965 1895 1895 1650 1650 ma i mbref4 (v dd ) x36 2155 2155 1915 1915 1665 1665 i mbref4 (v ext ) 130 130 115 115 105 105 operating burst write current : bl2 bl = 2; cyclic bank access; half of address bits change every clock cy- cle; continuous data; measure- ment is taken during continuous write i dd2w (v dd ) x18 2110 2110 1910 1910 1665 1665 ma i dd2w (v dd ) x36 2290 2290 2070 2070 1805 1805 i dd2w (v ext ) 80 80 75 75 70 70 operating burst write current : bl4 bl = 4; cyclic bank access; half of address bits change every two clock cycles; continuous data; measurement is taken during con- tinuous write i dd4w (v dd ) x18 1730 1730 1590 1590 1395 1395 ma i dd4w (v dd ) x36 1815 1815 1665 1665 1460 1460 i dd4w (v ext ) 55 55 55 55 50 50 operating burst write current :bl8 bl = 8; cyclic bank access; half of address bits change every four clock cycles; continuous data; measurement is taken during con- tinuous write i dd8w (v dd ) x18 1475 1475 1335 1335 1190 1190 ma i dd8w (v dd ) x36 na na na na na na i dd8w (v ext ) 45 45 40 40 40 40 multibank write current: dual bank write bl = 4; cyclic bank access using du- al bank write; half of address bits change every two clock cycles; con- tinuous data; measurement is tak- en during continuous write i dbwr (v dd ) x18 2305 2305 2170 2170 1885 1885 ma i dbwr (v dd ) x36 2400 2400 2250 2250 1960 1960 i dbwr (v ext ) 80 80 75 75 70 70 draft 12/19/2011 576mb: x18, x36 rldram 3 electrical characteristics C i dd specifications integrated silicon solution, inc. ? www.issi.com 01/17/2012 18
table 4: i dd operating conditions and maximum limits (continued) notes 1C6 apply to the entire table description condition symbol -093e -093 -107e -107 -125e -125 units notes multibank write current: quad bank write bl=4; cyclic bank access using quad bank write; half of address bits change every two clock cycles; continuous data; measurement is taken during continuous write; subject to t sa w specification i qbwr (v dd ) x18 2965 2965 2890 2890 2525 2525 ma i qbwr (v dd ) x36 3195 3195 3000 3000 2615 2615 i qbwr (v ext ) 130 130 115 115 100 100 operating burst read current example bl = 2; cyclic bank access; half of address bits change every clock cy- cle; continuous data; measure- ment is taken during continuous read i dd2r (v dd ) x18 2250 2250 2045 2045 1785 1785 ma i dd2r (v dd ) x36 2395 2395 2180 2180 1895 1895 i dd2r (v ext ) 80 80 75 75 70 70 operating burst read current example bl = 4; cyclic bank access; half of address bits change every two clock cycles; continuous data; measurement is taken during con- tinuous read i dd4r (v dd ) x18 1740 1740 1595 1595 1400 1400 ma i dd4r (v dd ) x36 1835 1835 1685 1685 1475 1475 i dd4r (v ext ) 55 55 55 55 50 50 operating burst read current example bl = 8; cyclic bank access; half of address bits change every four clock cycles; continuous data; measurement is taken during con- tinuous read i dd8r (v dd ) x18 1450 1450 1315 1315 1175 1175 ma i dd8r (v dd ) x36 na na na na na na i dd8r (v ext ) 45 45 40 40 40 40 draft 12/19/2011 576mb: x18, x36 rldram 3 electrical characteristics C i dd specifications integrated silicon solution, inc. ? www.issi.com 01/17/2012 19
notes: 1. i dd specifications are tested after the device is properly initialized. 0c t c +95c; +1.28v v dd +1.42v,+1.14v v ddq +1.26v,+2.38v v ext +2.63v,v ref = v ddq /2. 2. i dd mesurements use t ck (min), t rc (min), and minimum data latency (rl and wl). 3. input slew rate is 1v/ns for single ended signals and 2v/ns for differential signals. 4. definitions for i dd conditions: ? low is defined as v in v il(ac)max . ? high is defined as v in v ih(ac)min . ? continuous data is defined as half the dq signals changing between high and low every half clock cycle (twice per clock). ? continuous address is defined as half the address signals changing between high and low every clock cycle (once per clock). ? sequential bank access is defined as the bank address incrementing by one every t rc. ? cyclic bank access is defined as the bank address incrementing by one for each com- mand access. for bl = 2 this is every clock, for bl = 4 this is every other clock, and for bl = 8 this is every fourth clock. 5. cs# is high unless a read, write, aref, or mrs command is registered. cs# never tran- sitions more than once per clock cycle. 6. i dd parameters are specified with odt disabled. 7. upon exiting standby current conditions, at least one nop command must be issued with stable clock prior to issuing any other valid command. 576mb: x18, x36 rldram 3 electrical characteristics C i dd specifications integrated silicon solution, inc. ? www.issi.com 01/17/2012 20
electrical specifications C absolute ratings and i/o capacitance absolute maximum ratings s tresses greater than those listed may cause per manent damage to the device . this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. table 5: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss C0.4 1.975 v v ddq voltage on v ddq supply relative to v ss C0.4 1.66 v v in ,v out voltage on any ball relative to v ss C0.4 1.66 v v ext voltage on v ext supply relative to v ss C0.4 2.8 v input/output capacitance table 6: input/output capacitance notes 1-2 apply to entire table capacitance parameters symbol rl3-2133 rl3-1866 rl3-1600 units notes min max min max min max ck/ck# c ck 1.3 2.1 1.3 2.1 1.3 2.2 pf c: ck to ck# c dck 0 0.15 0 0.15 0 0.15 pf single-ended i/o: dq, dm c io 1.9 2.9 1.9 3.0 2.0 3.1 pf 3 input strobe: dk/dk# c io 1.9 2.9 1.9 3.0 2.0 3.1 pf output strobe: qk/qk#, qvld c io 1.9 2.9 1.9 3.0 2.0 3.1 pf c: dk to dk# c ddk 0 0.15 0 0.15 0 0.15 pf c: qk to qk# c dqk 0 0.15 0 0.15 0 0.15 pf c: dq to qk or dq to dk c dio C0.5 0.3 C0.5 0.3 C0.5 0.3 pf 4 inputs (cmd, addr) c i 1.25 2.25 1.25 2.25 1.25 2.25 pf 5 c: cmd_addr to ck c di_cmd_addr C0.5 0.3 C0.5 0.3 C0.4 0.4 pf 6 jtag balls c jt ag 1.5 4.5 1.5 4.5 1.5 4.5 pf 7 reset#, mf balls c i C 3.0 C 3.0 C 3.0 pf notes: 1. +1.28v v dd +1.42v, +1.14v v ddq 1.26v, +2.38v v ext +2.63v,v ref = v ss , f = 100 mhz, t c = 25c, v out(dc) = 0.5 v ddq , v out (peak-to-peak) = 0.1v. 2. capacitance is not tested on zq ball. 3. dm input is grouped with the i/o balls, because they are matched in loading. 4. c dio = c io(dq) - 0.5 (c io [qk] + c io [qk#]). 5. includes cs#, ref#, we#, a[19:0], and ba[3:0]. 6. c di_cmd_addr = c i (cmd_addr) - 0.5 (c ck [ck] + c ck [ck#]). 7. jtag balls are tested at 50 mhz. 576mb: x18, x36 rldram 3 electrical specifications C absolute ratings and i/o capaci- tance integrated silicon solution, inc. ? www.issi.com 01/17/2012 21
ac and dc operating conditions table 7: dc electrical characteristics and operating conditions note 1 applies to the entire table; unless otherwise noted: 0c t c +95c; +1.28v v dd +1.42v description symbol min max units notes supply voltage v ext 2.38 2.63 v supply voltage v dd 1.28 1.42 v isolated output buffer supply v ddq 1.14 1.26 v reference voltage v ref 0.49 v ddq 0.51 v ddq v 2, 3 input high (logic 1) voltage v ih(dc) v ref + 0.10 v ddq v input low (logic 0) voltage v il(dc) v ss v ref - 0.10 v input leakage current: any input 0v v in v dd , v ref ball 0v v in 1.1v (all other balls not under test = 0v) i li C2 2 a reference voltage current i ref C5 5 a notes: 1. all voltages referenced to v ss (gnd). 2. the nominal value of v ref is expected to be 0.5 v ddq of the transmitting device. v ref is expected to track variations in v ddq . 3. peak-to-peak noise (non-common mode) on v ref may not exceed 2% of the dc value. dc values are determined to be less than 20 mhz. peak-to-peak ac noise on v ref should not exceed 2% of v ref(dc) . thus, from v ddq /2, v ref is allowed 2% v ddq /2 for dc error and an additional 2% v ddq /2 for ac noise. the measurement is to be taken at the nearest v ref bypass capacitor . t able 8: input ac logic levels notes 1-3 apply to entire table; unless otherwise noted: 0c t c +95c; +1.28v v dd +1.42v description symbol min max units input high (logic 1) voltage v ih(ac) v ref + 0.15 C v input low (logic 0) voltage v il(ac) C v ref - 0.15 v notes: 1. all voltages referenced to v ss (gnd). 2. the receiver will ef fectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above/below the dc input low/high level. 3. single-ended input slew rate = 1 v/ns; maximum input voltage swing under test is 900mv (peak-to-peak). 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 22
figure 6: single-ended input signal 0.450v 0.0v 0.50v 0.576v 0.588v 0.60v 0.612v 0.624v 0.70v 0.750v v il(ac) v il(dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih(dc) v ih(ac) 1.20v 1.60v C0.40v v ddq v ddq + 0.4v narrow pulse width v ss - 0.4v narrow pulse width v ss 0.45v 0.50v 0.576v 0.588v 0.60v 0.612v 0.624v 0.70v 0.750v minimum v il and v ih levels v ih(dc) v ih(ac) v il(ac) v il(dc) v il and v ih levels with ringback 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 23
ac overshoot/undershoot specifications table 9: control and address balls parameter rl3-2133 rl3-1866 rl3-1600 maximum peak amplitude allowed for overshoot area 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area 0.4v 0.4v 0.4v maximum overshoot area above v ddq 0.25 vns 0.28 vns 0.33 vns maximum undershoot area below v ss /v ssq 0.25 vns 0.28 vns 0.33 vns table 10: clock, data, strobe, and mask balls parameter rl3-2133 rl3-1866 rl3-1600 maximum peak amplitude allowed for overshoot area 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area 0.4v 0.4v 0.4v maximum overshoot area above v ddq 0.10 vns 0.11 vns 0.13 vns maximum undershoot area below v ss /v ssq 0.10 vns 0.11 vns 0.13 vns figure 7: overshoot maximum amplitude overshoot area v ddq time (ns) volts (v) figure 8: undershoot maximum amplitude undershoot area v ss /v ssq time (ns) volts (v) 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 24
table 11: differential input operating conditions (ck, ck# and dk x, dkx#) notes 1 and 2 apply to entire table parameter/condition symbol min max units notes differential input voltage logic high C slew v ih,dif f_slew +200 n/a mv 3 dif ferential input voltage logic low C slew v il,dif f_slew n/a -200 mv 3 differential input voltage logic high v ih,dif f(ac) 2 (v ih(ac) - v ref ) v ddq mv 4 differential input voltage logic low v il,dif f(ac) v ssq 2 (v il(ac) - v ref ) mv 5 differential input crossing voltage relative to v dd /2 v ix v ref(dc) - 150 v ref(dc) + 150 mv 6 single-ended high level v seh v ih(ac) v ddq mv 4 single-ended low level v sel v ssq v il(ac) mv 5 notes: 1. ck/ck# and dk x /dk x # are referenced to v ddq and v ssq . 2. differential input slew rate = 2 v/ns. 3. defines slew rate reference points, relative to input crossing voltages. 4. maximum limit is relative to single-ended signals; overshoot specifications are applica- ble. 5. minimum limit is relative to single-ended signals; undershoot specifications are applica- ble. 6. the typical value of v ix is expected to be about 0.5 v ddq of the transmitting device and v ix is expected to track variations in v ddq . v ix indicates the voltage at which differ- ential input signals must cross. figure 9: v ix for differential signals ck, dkx v ddq /2 v ddq /2 v ix v ix ck#, dkx# v ddq ck, dkx v ddq v ssq ck#, dkx# v ssq x x x x v ix v ix 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 25
figure 10: single-ended requirements for differential signals v ss v ddq v sel,max v seh,min v seh v sel v ddq /2 ck or dk x figure 11: definition of differential ac swing and t dv ac v ih,diff(ac)min v ih,diff_slew,min 0.0 v il,diff_slew,max t dvac half cycle t dv ac ck - ck# dkx - dkx# v il,diff(ac)max 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 26
table 12: allowed time before ringback ( t dvac) for ck, ck#, dk x, and dk x # slew rate (v/ns) min t dv ac (ps) at |v ih /v il,dif f(ac) | >4.0 175 4.0 170 3.0 167 2.0 163 1.9 162 1.6 161 1.4 159 1.2 155 1.0 150 <1.0 150 slew rate definitions for single-ended input signals setup ( t is and t ds) nominal slew rate for a rising signal is defined as the slew r ate be- tw een the last crossing of v ref and the first crossing of v ih(ac)min . setup ( t is and t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref and the first crossing of v il(ac)max . hold ( t ih and t dh) nominal slew rate for a rising signal is defined as the slew rate be- tween the last crossing of v il(dc)max and the first crossing of v ref . hold ( t ih and t dh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref (see figure 12 (page 28)). table 13: single-ended input slew rate definition input slew rates (linear signals) measured calculation input edge from to setup rising v ref v ih(ac)min [v ih(ac)min - v ref ]/trs falling v ref v il(ac)max [v ref - v il(ac)max ]/tfs hold rising v il(dc)max v ref [v ref - v il(dc)max ]/trh falling v ih(dc)min v ref [v ih(dc)min - v ref ]/tfh 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 27
figure 12: nominal slew rate definition for single-ended input signals trs tfs trh tfh v ref v ref v ih(ac)min v il(ac)max v il(ac)max v ih(ac)min v ih(dc)min v il(dc)max v il(dc)max v ih(dc)min setup hold single-ended input voltage (dq, cmd, addr) single-ended input voltage (dq, cmd, addr) 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 28
slew rate definitions for differential input signals input slew rate for differential signals (ck, ck# and dk x , dkx #) are defined and meas- ured as shown in the following two tables. the nominal slew rate for a rising signal is defined as the slew rate between v il,diff,max and v ih,diff,min . the nominal slew rate for a falling signal is defined as the slew rate between v ih,diff,min and v il,diff,max . table 14: differential input slew rate definition differential input slew rates (linear signals) measured calculation input edge from to ck and dk reference rising v il,dif f_slew ,max v ih,dif f_slew ,min [v ih,dif f_slew,min - v il,dif f_slew,max ]/ tr diff falling v ih,diff_slew,min v il,diff_slew,max [v ih,dif f_slew,min - v il,dif f_slew,max ]/ tf diff figure 13: nominal differential input slew rate definition for ck, ck#, dk x, and dkx# tr diff tf diff v ih,diff_slew,min v il,diff_slew,max 0 differential input voltage (ck, ck#; dkx, dkx#) 576mb: x18, x36 rldram 3 ac and dc operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 29
odt characteristics odt effective resistance, r t t , is defined b y mr1[4:2]. odt is applied to the dq, dm, and dkx, dkx # balls. the individual pull-up and pull-down resistors (r ttpu and r ttpd ) are defined as follows: r ttpu =(v ddq - v out ) / |i out |, under the condition that r ttpd is turned off r ttpd = (v out ) / |i out |, under the condition that r ttpu is turned off figure 14: odt levels and i-v characteristics r ttpu r ttpd odt chip in termination mode v ddq dq v ssq i out = i pd - i pu i pu i pd i out v out to other circuitry such as rcv, . . . table 15: odt dc electrical characteristics parameter/condition symbol min nom max units notes r tt effective impedance from v il(ac) to v ih(ac) r tt_eff see table 16 (page 31). 1, 2 deviation of v m with respect to v ddq /2 vm -5 - +5 % 3 notes: 1. tolerance limits are applicable after proper zq calibration has been performed at a sta- ble temperature and voltage. refer to odt sensitivity (page 32) if either the tempera- ture or voltage changes after calibration. 2. measurement definition for r tt : apply v ih(ac) to ball under test and measure current i[v ih(ac) ], then apply v il(ac) to ball under test and measure current i[v il(ac) ]: v ih(ac) - v il(ac) |i[v ih(ac) ] - i[v il(ac) ]| r tt 3. measure voltage (v m ) at the tested ball with no load: 2 vm v ddq vm - 1 100 odt resistors the on-die termination resistance is selected by mr1[4:2]. the follo wing table provides an overview of the odt dc electrical characteristics. the values provided are not speci- 576mb: x18, x36 rldram 3 odt characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 30
fication requirements; however, they can be used as design guidelines to indicate what r tt is targeted to pro vide: ? r tt 120 is made up of r tt120(pd240) and r tt120(pu240) . ? r tt 60 is made up of r tt60(pd120) and r tt60(pu120) . ? r tt 40 is made up of r tt40(pd80) and r tt40(pu80) . table 16: r tt effective impedances r tt resistor v out min nom max units 120 r tt120(pd240) 0.2 x v ddq 0.6 1.0 1.1 rzq/1 0.5 x v ddq 0.9 1.0 1.1 rzq/1 0.8 x v ddq 0.9 1.0 1.4 rzq/1 r tt120(pu240) 0.2 x v ddq 0.9 1.0 1.4 rzq/1 0.5 x v ddq 0.9 1.0 1.1 rzq/1 0.8 x v ddq 0.6 1.0 1.1 rzq/1 120 v il(ac) to v ih(ac) 0.9 1.0 1.6 rzq/2 60 r tt60(pd120) 0.2 x v ddq 0.6 1.0 1.1 rzq/2 0.5 x v ddq 0.9 1.0 1.1 rzq/2 0.8 x v ddq 0.9 1.0 1.4 rzq/2 r tt60(pu120) 0.2 x v ddq 0.9 1.0 1.4 rzq/2 0.5 x v ddq 0.9 1.0 1.1 rzq/2 0.8 x v ddq 0.6 1.0 1.1 rzq/2 60 v il(ac) to v ih(ac) 0.9 1.0 1.6 rzq/4 40 r tt40(pd80) 0.2 x v ddq 0.6 1.0 1.1 rzq/3 0.5 x v ddq 0.9 1.0 1.1 rzq/3 0.8 x v ddq 0.9 1.0 1.4 rzq/3 r tt40(pu80) 0.2 x v ddq 0.9 1.0 1.4 rzq/3 0.5 x v ddq 0.9 1.0 1.1 rzq/3 0.8 x v ddq 0.6 1.0 1.1 rzq/3 40 v il(ac) to v ih(ac) 0.9 1.0 1.6 rzq/6 576mb: x18, x36 rldram 3 odt characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 31
odt sensitivity if either temperature or v oltage changes after i/o calibr ation, then the tolerance limits listed in table 15 (page 30) and table 16 (page 31) can be expected to widen according to table 17 (page 32) and table 18 (page 32). table 17: odt sensitivity definition symbol min max units r tt 0.9 - dr tt dt |dt| - dr tt dv |dv| 1.6 + dr tt dt |dt| + dr tt dv | dv| rzq/(2,4,6) note: 1. dt = t - t(@ calibration), dv = v ddq - v ddq (@ calibration) or v dd - v dd (@ calibration). t able 18: odt t emperatur e and v oltage sensitivity change min max units dr tt dt 0 1.5 %/c dr tt dv 0 0.15 %/mv 576mb: x18, x36 rldram 3 odt characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 32
output driver impedance the output driver impedance is selected by mr1[1:0] dur ing initialization. the selected value is able to maintain the tight tolerances specified if proper zq calibration is per- formed. output specifications refer to the default output driver unless specifically stated other- wise. a functional representation of the output buffer is shown below. the output driver impedance r on is defined by the value of the external reference resistor rzq as follows: ? r on,x = rzq/ y (with rzq = 240 x or 60 with y = 6 or 4, respectively) the individual pull-up and pull-down resistors (r on(pu) and r on(pd) ) are defined as fol- lows: ? r on(pu) = (v ddq - v out )/|i out |, when r on(pd) is turned off ? r on(pd) = (v out )/|i out |, when r on(pu) is turned off figure 15: output driver r on(pu) r on(pd) chip in drive mode output driver v ddq dq v ssq i pu i pd i out v out to other circuitry such as rcv, . . . 576mb: x18, x36 rldram 3 output driver impedance integrated silicon solution, inc. ? www.issi.com 01/17/2012 33
table 19: driver pull-up and pull-down impedance calculations r on min nom max units rzq/6 = (240 39.6 40 40.4 rzq/4 = (240 59.4 60 60.6 driver v out min nom max units pull-down 0.2 v ddq 24 40 44 0.5 v ddq 36 40 44 0.8 v ddq 36 40 56 pull-up 0.2 v ddq 36 40 56 0.5 v ddq 36 40 44 0.8 v ddq 24 40 44 pull-down 0.2 v ddq 36 60 66 0.5 v ddq 54 60 66 0.8 v ddq 54 60 84 pull-up 0.2 v ddq 54 60 84 0.5 v ddq 54 60 66 0.8 v ddq 36 60 66 576mb: x18, x36 rldram 3 output driver impedance integrated silicon solution, inc. ? www.issi.com 01/17/2012 34
output driver sensitivity if either the temperature or the v oltage changes after z q calibration, then the tolerance limits listed in table 19 (page 34) can be expected to widen according to table 20 (page 35) and table 21 (page 35). table 20: output driver sensitivity definition symbol min max units r on(pd) @ 0.2 v ddq 0.6 - dr on dth dt - dr on dvh dv 1.1 + dr on dth dt + dr on dvh dv rzq/(6, 4) r on(pd) @ 0.5 v ddq 0.9 - dr on dtm dt - dr on dvm dv 1.1 + dr on dtm dt + dr on dvm dv rzq/(6, 4) r on(pd) @ 0.8 v ddq 0.9 - dr on dtl dt - dr on dvl dv 1.4 + dr on dtl dt + dr on dvl d rzq/(6, 4) r on(pu) @ 0.2 v ddq 0.9 - dr on dth dt - dr on dvh dv 1.4 + dr on dth dt + dr on dvh dv rzq/(6, 4) r on(pu) @ 0.5 v ddq 0.9 - dr on dtm dt - dr on dvm dv 1.1 + dr on dtm dt + dr on dvm dv rzq/(6, 4) r on(pu) @ 0.8 v ddq 0.6 - dr on dtl dt - dr on dvl dv 1.1 + dr on dtl dt + dr on dvl dv rzq/(6, 4) note: 1. dt = t - t(@ calibration), dv = v ddq - v ddq (@ calibration) or v dd - v dd (@ calibration). t able 21: output driver v oltage and t emperatur e sensitivity change min max unit dr on dtm 0 1.5 %/c dr on dvm 0 0.15 %/mv dr on dtl 0 1.5 %/c dr on dvl 0 0.15 %/mv dr on dth 0 1.5 %/c dr on dvh 0 0.15 %/mv 576mb: x18, x36 rldram 3 output driver impedance integrated silicon solution, inc. ? www.issi.com 01/17/2012 35
output characteristics and operating conditions table 22: single-ended output driver characteristics note 1 and 2 apply to entire table parameter/condition symbol min max units notes output leakage current; dq are disabled; any output ball 0v v out v ddq ; odt is disabled; all other balls not under test = 0v i oz C5 5 a output slew rate: single-ended; for rising and falling edges, measures between v ol(ac) = v ref - 0.1 v ddq and v oh(ac) = v ref + 0.1 v ddq srq se 2.5 6 v/ns 4, 5 single-ended dc high-level output voltage v oh(dc) 0.8 v ddq v 6 single-ended dc mid-point level output voltage v om(dc) 0.5 v ddq v 6 single-ended dc low-level output voltage v ol(dc) 0.2 v ddq v 6 single-ended ac high-level output voltage v oh(ac) v tt + 0.1 v ddq v 7, 8, 9 single-ended ac low-level output voltage v ol(ac) v tt - 0.1 v ddq v 7, 8, 9 impedance delta between pull-up and pull-down for dq and qvld mm pupd C10 10 % 3 test load for ac timing and output slew rates output to v tt (v ddq /2) via 25 resistor 9 notes: 1. all voltages are referenced to v ss . 2. rzq is 240 (1%) and is applicable after proper zq calibration has been performed at a stable temperature and voltage. 3. measurement definition for mismatch between pull-up and pull-down (mm pupd ). meas- ure both r on(pu) and r on(pd) at 0.5 v ddq : ron pu - ron pd ron nom mm pupd x 100 4. the 6 v/ns maximum is applicable for a single dq signal when it is switching either from high to low or low to high while the remaining dq signals in the same byte lane are either all static or switching the opposite direction. for all other dq signal switching combinations, the maximum limit of 6 v/ns is reduced to 5 v/ns. 5. see table 24 (page 40) for output slew rate. 6. see the driver pull-up and pull-down impedance calculations table for iv curve linearity. do not use ac test load. 7. v tt = v ddq /2 8. see figure 16 (page 38) for an example of a single-ended output signal. 9. see figure 18 (page 39) for the test load configuration. 576mb: x18, x36 rldram 3 output characteristics and operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 36
table 23: differential output driver characteristics notes 1 and 2 apply to entire table parameter/condition symbol min max units notes output leakage current; dq are disabled; any output ball 0v v out v ddq ; odt is disabled; all other balls not under test = 0v i oz C5 5 a output slew rate: differential; for rising and falling edges, measures between v ol,dif f(ac) = C0.2 v ddq and v oh,dif f(ac) = +0.2 v ddq srq dif f 5 12 v/ns 5 output differential cross-point voltage v ox(ac) v ref - 150 v ref + 150 mv 6 differential high-level output voltage v oh,diff(ac) +0.2 v ddq v 6 differential low-level output voltage v ol,diff(ac) C0.2 v ddq v 6 delta resistance between pull-up and pull-down for qk/qk# mm pupd C10 10 % 3 t est load for ac timing and output slew rates output to v tt (v ddq /2) via 25 resistor 4 notes: 1. all voltages are referenced to v ss . 2. rzq is 240 (1%) and is applicable after proper zq calibration has been performed at a stable temperature and voltage. 3. measurement definition for mismatch between pull-up and pull-down (mm pupd ). meas- ure both r on(pu) and r on(pd) at 0.5 x v ddq : ron pu - ron pd ron nom mm pupd x 100 4. see figure 18 (page 39) for the test load configuration. 5. see table 25 (page 41) for the output slew rate. 6. see figure 17 (page 39) for an example of a differential output signal. 576mb: x18, x36 rldram 3 output characteristics and operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 37
figure 16: dq output signal v oh(ac) min output max output v ol(ac) 576mb: x18, x36 rldram 3 output characteristics and operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 38
figure 17: differential output signal v oh,diff min output max output v ol,diff v ox(ac)max v ox(ac)min x x x x reference output load the following figure represents the effective reference load of 25 used in defining the relevant device ac timing parameters as well as the output slew rate measurements. it is not intended to be a precise representation of a particular system environment or a de- piction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system envi- ronment. figure 18: reference output load for ac timing and output slew rate timing reference point dq qkx qkx# qvld dut v ref v tt = v ddq /2 v ddq /2 zq rzq = 240 v ss r tt = 25 576mb: x18, x36 rldram 3 output characteristics and operating conditions integrated silicon solution, inc. ? www.issi.com 01/17/2012 39
slew rate definitions for single-ended output signals the single-ended output driver is summariz ed in the follo wing table. with the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between v ol(ac) and v oh(ac) for single-ended signals. table 24: single-ended output slew rate definition single-ended output slew rates (linear signals) measured calculation output edge from to dq and qvld rising v ol(ac) v oh(ac) v oh(ac) - v ol(ac) tr se falling v oh(ac) v ol(ac) v oh(ac) - v ol(ac) tf se figure 19: nominal slew rate definition for single-ended output signals tr se tf se v oh(ac) v ol(ac) v tt 576mb: x18, x36 rldram 3 slew rate definitions for single-ended output signals integrated silicon solution, inc. ? www.issi.com 01/17/2012 40
slew rate definitions for differential output signals the differential output driver is summar iz ed in the following table. with the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between v ol(ac) and v oh(ac) for differential signals. table 25: differential output slew rate definition differential output slew rates (linear sig- nals) measured calculation output edge from to qkx, qkx# rising v ol,dif f(ac) v oh,diff(ac) v oh,diff(ac)max - v ol,diff(ac) tr diff falling v oh,diff(ac) v ol,diff(ac) v oh,diff(ac) - v ol,diff(ac) tf diff figure 20: nominal differential output slew rate definition for qkx, qkx# tr diff tf diff v oh,diff(ac) v ol,diff(ac) 0 576mb: x18, x36 rldram 3 slew rate definitions for differential output signals integrated silicon solution, inc. ? www.issi.com 01/17/2012 41
speed bin tables table 26: rl3 speed bins parameter symbol -093e -093 -107e -107 125e -125 units min max min max min max min max min max min max clock timing rl = 3 ; wl = 4 t ck (avg) 5 5 5 5 reserved reserved reserved reserved ns rl = 4 ; wl = 5 t ck (avg) 4 5 4 5 4 5 4 5 4 5 5 5 ns rl = 5 ; wl = 6 t ck (avg) 3 4.3 3 4.3 3.5 4.3 4 4.3 4 4.3 4 5 ns rl = 6 ; wl = 7 t ck (avg) 2.5 3.5 2.5 4 3 3.5 3 4.3 3 4.3 3.5 4.3 ns rl = 7 ; wl = 8 t ck (avg) 2.5 3 2.5 3 2.5 3 2.5 3 2.5 3 3 3.5 ns rl = 8 ; wl = 9 t ck (avg) 1.875 2.5 1.875 3 2 2.5 2 3 2 3 2.5 3 ns rl = 9 ; wl = 10 t ck (avg) 1.875 2 1.875 2 1.875 2 1.875 2 1.875 2 2.33 2.66 ns rl = 10 ; wl = 11 t ck (avg) 1.5 2 1.5 2 1.875 2 1.875 2 1.875 2 2 2.33 ns rl = 11 ; wl = 12 t ck (avg) 1.5 1.875 1.5 2 1.5 1.875 1.5 2 1.5 2 1.875 2.33 ns rl = 12 ; wl = 13 t ck (avg) 1.25 1.5 1.25 1.875 1.5 1.66 1.5 1.875 1.5 1.875 1.875 2 ns rl = 13 ; wl = 14 t ck (avg) 1.25 1.5 1.25 1.5 1.25 1.5 1.25 1.5 1.25 1.5 1.5 1.875 ns rl = 14 ; wl = 15 t ck (avg) 1.07 1.25 1.07 1.5 1.25 1.33 1.25 1.5 reserved 1.4 1.66 ns rl = 15 ; wl = 16 t ck (avg) 1.0 1.25 1.0 1.25 1.07 1.33 1.07 1.25 reserved 1.33 1.66 ns rl = 16 ; wl = 17 t ck (avg) 0.935 1.25 0.935 1.25 reserved reserved reserved 1.25 1.33 ns row cycle timing row cycle time t rc 8 - 10 - 8 - 10 - 10 - 12 - ns note: 1. the min t ck value for a given rl/wl parameter must be used to determine the t rc mode register setting. 576mb: x18, x36 rldram 3 speed bin tables integrated silicon solution, inc. ? www.issi.com 01/17/2012 42
ac electrical characteristics table 27: ac electrical characteristics notes 1C7 apply to entire table parameter symbol rl3C2133 rl3C1866 rl3C1600 units notes min max min max min max clock timing clock period average: dll disable mode t ck(dll_dis ) 8 488 8 488 8 488 ns 8 clock period average: dll en- able mode t ck(avg) see t ck values in the rl3 speed bins table. ns 9, 10 high pulse width average t ch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 ck 11 low pulse width average t cl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 ck 11 clock period jitter dll locked t jit(per) C50 50 C60 60 C70 70 ps 12 dll locking t jit(per),lck C40 40 C50 50 C60 60 ps 12 clock absolute period t ck(abs) min = t ck(avg),min + t jit(per),min; max = t ck(avg),max + t jit(per),max ps clock absolute high pulse width t ch(abs) 0.43 C 0.43 C 0.43 C t ck(avg) 13 clock absolute low pulse width t cl(abs) 0.43 C 0.43 C 0.43 C t ck(avg) 14 cycle-to- cycle jitter dll locked t jit(cc) 100 120 140 ps 15 dll locking t jit(cc),lck 80 100 120 ps 15 cumulative error across 2 cycles t err(2per) C74 74 C88 88 C103 103 ps 16 3 cycles t err(3per) C87 87 C105 105 C122 122 ps 16 4 cycles t err(4per) C97 97 C117 117 C136 136 ps 16 5 cycles t err(5per) C105 105 C126 126 C147 147 ps 16 6 cycles t err(6per) C111 111 C133 133 C155 155 ps 16 7 cycles t err(7per) C116 116 C139 139 C163 163 ps 16 8 cycles t err(8per) C121 121 C145 145 C169 169 ps 16 9 cycles t err(9per) C125 125 C150 150 C175 175 ps 16 10 cycles t err(10per) C128 128 C154 154 C180 180 ps 16 11 cycles t err(11per) C132 132 C158 158 C184 184 ps 16 12 cycles t err(12per) C134 134 C161 161 C188 188 ps 16 n = 13, 14 ... 49, 50 cycles t err(nper) t err(nper),min = [1 + 0.68ln(n)] t jit(per),min t err(nper),max = [1 + 0.68ln(n)] t jit(per),max ps 16 dq input timing data setup time to dk, dk# base (specification) t ds(ac150) C30 C C15 C 10 C ps 17, 18 v ref @ 1 v/ns 120 C 135 C 160 C ps 18, 19 576mb: x18, x36 rldram 3 ac electrical characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 43
table 27: ac electrical characteristics (continued) notes 1C7 apply to entire table parameter symbol rl3C2133 rl3C1866 rl3C1600 units notes min max min max min max data hold time from dk, dk# base (specification) t dh(dc100) 5 C 20 C 45 C ps 17, 18 v ref @ 1 v/ns 105 C 120 C 145 C ps minimum data pulse width t dipw 280 C 320 C 360 C ps 20 dq output timing qk, qk# edge to output data edge within byte group t qkq x C 75 C 85 C 100 ps qk, qk# edge to any output data edge within specific data word grouping (only for x36) t qkq02, t qkq13 C 125 C 135 C 150 ps 22 dq output hold time from qk, qk# t qh 0.38 C 0.38 C 0.38 C t ck(avg) 23 dq low-z time from ck, ck# t lz C360 180 C390 195 C450 225 ps 24, 26 dq high-z time from ck, ck# t hz C 180 C 195 C 225 ps 24, 26 input and output strobe timing dk (rising), dk# (falling) edge to/from ck (rising), ck# (fall- ing) edge t ckdk C0.27 0.27 C0.27 0.27 C0.27 0.27 ck 29 dk, dk# differential input high width t dkh 0.45 0.55 0.45 0.55 0.45 0.55 ck dk, dk# differential input low width t dkl 0.45 0.55 0.45 0.55 0.45 0.55 ck qk (rising), qk# (falling) edge to ck (rising), ck# (falling) edge t ckqk C135 - 5% tck 135 + 5% tck C140 - 5% tck 140 + 5% tck C160 - 5% tck 160 + 5% tck ps 26 qk (rising), qk# (falling) edge to ck (rising), ck# (falling) edge with dll disabled t ckqk dll_dis 1 10 1 10 1 10 ns 27 qk, qk# differential output high time t qkh 0.4 C 0.4 C 0.4 C ck 23 qk, qk# differential output low time t qkl 0.4 C 0.4 C 0.4 C ck 23 qk (falling), qk# (rising) edge to qvld edge t qkvld C 125 C 135 C 150 ps 25 command and address timing ctrl, cmd, addr, set- up to ck,ck# base (specification) t is(ac150) 85 C 120 C 170 C ps 28, 30 v ref @ 1 v/ns 235 C 270 C 320 C ps 19, 30 576mb: x18, x36 rldram 3 ac electrical characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 44
table 27: ac electrical characteristics (continued) notes 1C7 apply to entire table parameter symbol rl3C2133 rl3C1866 rl3C1600 units notes min max min max min max ctrl, cmd, addr, hold from ck,ck# base (specification) t ih(dc100) 65 C 100 C 120 C ps 28, 30 v ref @ 1 v/ns 165 C 200 C 220 C ps 19, 30 minimum ctrl, cmd, addr pulse width t ipw 470 C 535 C 560 C ps 20 row cycle time t rc see minimum t rc values in the rl3 speed bins table. ns 21 refresh rate t ref 64 C 64 C 64 C ms sixteen-bank access window t sa w 8 C 8 C 8 C ns multibank access delay t mmd 2 C 2 C 2 C ck 33 write-to-read to same ad- dress t wtr wl + bl/2 C wl + bl/2 C wl + bl/2 C ns 32 mode register set cycle time to any command t mrsc 12 C 12 C 12 C ck read training register mini- mum read time t rtrs 2 C 2 C 2 C ck read training register burst end to mode register set for training register exit t rtre 1 C 1 C 1 C ck calibration timing zqcl: long calibration time power-up and reset operation t zqinit 512 C 512 C 512 C ck normal operation t zqoper 256 C 256 C 256 C ck zqcs: short calibration time t zqcs 64 C 64 C 64 C ck initialization and reset timing begin power-supply ramp to power supplies stable t v ddpr C 200 C 200 C 200 ms reset# low to power sup- plies stable t rps C 200 C 200 C 200 ms reset# low to i/o and r tt high-z t ioz C 20 C 20 C 20 ns 31 notes: 1. parameters are applicable with 0c t c +95c; +1.28v v dd +1.42v, +2.38v v ext +2.63v, +1.14v v ddq 1.26v. 2. all voltages are referenced to v ss . 3. the unit t ck(avg) represents the actual t ck(avg) of the input clock under operation. the unit ck represents one clock cycle of the input clock, counting the actual clock edges. 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 900mv in the test environ- ment, but input timing is still referenced to v ref (except t is, t ih, t ds, and t dh use the ac/dc trip points and ck,ck# and dkx, dkx# use their crossing points). the minimum slew rate for the input signals used to test the device is 1 v/ns for single-ended inputs and 2 v/ns for differential inputs in the range between v il(ac) and v ih(ac) . 576mb: x18, x36 rldram 3 ac electrical characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 45
5. all timings that use time-based values (ns, s, ms) should use t ck(avg) to determine the correct number of clocks. in the case of noninteger results, all minimum limits should be rounded up to the nearest whole integer, and all maximum limits should be rounded down to the nearest whole integer . 6. the term ?strobe? refers to the dk and dk# or qk and qk# differential crossing point when dk and qk, respectively, is the rising edge. clock, or ck, refers to the ck and ck# differential crossing point when ck is the rising edge. 7. the output load defined in figure 18 (page 39) is used for all ac timing and slew rates. the actual test load may be different. the output signal voltage reference point is v ddq /2 for single-ended signals and the crossing point for differential signals. 8. when operating in dll disable mode, issi does not warrant compliance with normal mode timings or functionality. 9. the clock?s t ck(avg) is the average clock over any 200 consecutive clocks and t ck(avg),min is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. input clock jitter is allowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 10. spread spectrum is not included in the jitter specification values. however, the input clock can accommodate spread spectrum at a sweep rate in the range of 20?60 khz with an additional 1% of t ck(avg) as a long-term jitter component; however, the spread spec- trum may not use a clock rate below t ck(avg),min. 11. the clock?s t ch(avg) and t cl(avg) are the average half-clock period over any 200 consec- utive clocks and is the smallest clock half-period allowed, with the exception of a devia- tion due to clock jitter. input clock jitter is allowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 12. the period jitter, t jit(per), is the maximum deviation in the clock period from the aver- age or nominal clock. it is allowed in either the positive or negative direction. 13. t ch(abs) is the absolute instantaneous clock high pulse width as measured from one ris- ing edge to the following falling edge. 14. t cl(abs) is the absolute instantaneous clock low pulse width as measured from one fall- ing edge to the following rising edge. 15. the cycle-to-cyle jitter, t jit(cc), is the amount the clock period can deviate from one cycle to the next. it is important to keep cycle-to-cycle jitter at a minimum during the dll locking time. 16. the cumulative jitter error, t err(nper), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 17. t ds(base) and t dh(base) values are for a single-ended 1 v/ns dq slew rate and 2 v/ns dif- ferential dk, dk# slew rate. 18. these parameters are measured from a data signal (dm, dq0, dq1, and so forth) transi- tion edge to its respective data strobe signal (dk, dk#) crossing. 19. the setup and hold times are listed converting the base specification values (to which derating tables apply) to v ref when the slew rate is 1 v/ns. these values, with a slew rate of 1 v/ns, are for reference only. 20. pulse width of an input signal is defined as the width between the first crossing of v ref(dc) and the consecutive crossing of v ref(dc) . 21. bits mr0[3:0] select the number of clock cycles required to satisfy the minimum t rc val- ue. minimum t rc value must be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge that the subsequent command can be issued to the bank. 22. t qkq02 defines the skew between qk0 and dq[26:18] and between qk2 and dq[8:0]. t qkq13 defines the skew between qk1 and dq[35:27] and between qk3 and dq[17:9]. 23. when the device is operated with input clock jitter, this parameter needs to be derated by the actual t jit(per) (the larger of t jit(per),min or t jit(per),max of the input clock; out- put deratings are relative to the sdram input clock). 576mb: x18, x36 rldram 3 ac electrical characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 46
24. single-ended signal parameter. 25. for x36 device this specification references the skew between the falling edge of qk0 and qk1 to qvld0 and the falling edge of qk2 and qk3 to qvld1. 26. the dram output timing is aligned to the nominal or average clock. the following out- put parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. this results in each parameter becoming larger . the following parameters are required to be derated by subtracting t err(10per),max: t ckqk (min), and t lz (min). the following parameters are required to be derated by subtracting t err(10per),min: t ckqk (max), t hz (max), and t lz (max). 27. the t dqsckdll_dis parameter begins rl - 1 cycles after the read command. 28. t is(base) and t ih(base) values are for a single-ended 1 v/ns control/command/address slew rate and 2 v/ns ck, ck# dif ferential slew rate. 29. these parameters are measured from the input data strobe signal (dk/dk#) crossing to its respective clock signal crossing (ck/ck#). the specification values are not affected by the amount of clock jitter applied as they are relative to the clock signal crossing. these parameters should be met whether or not clock jitter is present. 30. these parameters are measured from a command/address signal transition edge to its respective clock (ck, ck#) signal crossing. the specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. these parameters should be met whether or not clock jitter is present. 31. reset# should be low as soon as power starts to ramp to ensure the outputs are in high-z. until reset# is low, the outputs are at risk of driving and could result in exces- sive current, depending on bus activity. 32. if t wtr is violated, the data just written will not be read out when a read command is issued to the same address. whatever data was previously written to the address will be output with the read command. 33. this specification is defined as any bank command (read, write, aref) to a multi-bank command or a multi-bank command to any bank command. this specification only ap- plies to quad bank write, 3-bank aref and 4-bank aref commands. dual bank write, 2-bank aref, and all single bank access commands are not bound by this specification. 576mb: x18, x36 rldram 3 ac electrical characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 47
parameter symbol min max units notes storage temperature t stg -55 150 c 1 reliability junction temperature commercial t j(rel) - 110 c 2 industrial - 110 c 2 operating junction temperature commercial t j(op) 0 100 c 3 industrial -40 100 c 3 operating case temperature commercial t c 0 95 c 4, 5 industrial -40 95 c 4, 5 package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) fbga 2-layer 39.3 28.8 25.2 16.3 2.0 4-layer 22.0 17.2 15.9 10.3 note: 1. thermal impedance data is based on a number of samples from multiple lots, and should be viewed as a typical number . 576mb: x18, x36 rldram 3 temperature and thermal impedance characteristics temperature and thermal impedance characteristics it is imperative that the device?s temperature specifications be maintained in order to ensure that the junction temperature is in the proper operating range to meet data sheet specifications. an important way to maintain the proper junction temperature is to use the device?s thermal impedances correctly. thermal impedances are listed for the available packages. incorrectly using thermal impedances can produce significant errors. the device?s safe junction temperature range can be maintained when the t c specifica- tion is not exceeded. in applications where the device?s ambient temperature is too high, use of forced air and/or heat sinks may be required in order to meet the case tem- perature specifications. table 28: temperature limits notes: 1. max storage case temperature; t stg is measured in the center of the package (see fig- ure 21 (page 49)). this case temperature limit is allowed to be exceeded briefly during package reflow. 2. temperatures greater than 110c may cause permanent damage to the device. this is a stress rating only and functional operation of the device at or above this is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect the reliability of the part. 3. junction temperature depends upon package type, cycle time, loading, ambient temper- ature, and airflow. 4. max operating case temperature; t c is measured in the center of the package (see fig- ure 21 (page 49)). 5. device functionality is not guaranteed if the device exceeds maximum t c during opera- tion. table 29: thermal impedance integrated silicon solution, inc. ? www.issi.com 01/17/2012 48
figure 21: example temperature test point location 13.5mm 6.75mm test point 13.5mm 6.75mm 576mb: x18, x36 rldram 3 temperature and thermal impedance characteristics integrated silicon solution, inc. ? www.issi.com 01/17/2012 49
command and address setup, hold, and derating the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is (base) and t ih (base) v alues (see t able 30 (page 50); values come from ta- ble 27 (page 43)) to the t is and t ih derating values (see table 31 (page 51)), respec- tively. example: t is (total setup time) = t is (base) + t is. for a valid transition, the input signal must remain above/below v ih(ac) /v il(ac) for some time t vac (see table 32 (page 51)). although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached v ih(ac) /v il(ac) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach v ih(ac) / v il(ac) . for slew rates which fall between the values listed in table 31 (page 51) and table 32 (page 51) for valid transition, the derating values may be obtained by linear interpolation. setup ( t is) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup ( t is) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between the shaded v ref(dc) -to-ac region, use the nominal slew rate for derat- ing value (see figure 22 (page 52)). if the actual signal is later than the nominal slew rate line anywhere between the shaded v ref(dc) -to-ac region, the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for derating value (see figure 24 (page 54)). hold ( t ih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . hold ( t ih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between the shaded dc-to-v ref(dc) region, use the nominal slew rate for derat- ing value (see figure 23 (page 53)). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded dc-to-v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to the v ref(dc) level is used for derating value (see figure 25 (page 55)). table 30: command and address setup and hold values referenced at 1 v/ns C ac/dc-based symbol rl3-2133 rl3-1866 rl3-1600 units reference t is(base),ac150 85 120 170 ps v ih(ac) /v il(ac) t ih(base),dc100 65 100 120 ps v ih(dc) /v il(dc) 576mb: x18, x36 rldram 3 command and address setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 50
table 31: derating values for t is/ t ih C ac150/dc100-based t is, t ih derating (ps) - ac/dc-based ac 150 thr eshold: v ih(ac) = v ref(dc) + 150mv , v il(ac) = v ref(dc) - 150mv cmd/addr slew rate (v/ns) ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 C4 0 C4 0 C4 8 4 16 12 24 20 32 30 40 46 0.8 0 C10 0 C10 0 C10 8 C2 16 6 24 14 32 24 40 40 0.7 0 C16 0 C16 0 C16 8 C8 16 0 24 8 32 18 40 34 0.6 C1 C26 C1 C26 C1 C26 7 C18 15 C10 23 C2 31 8 39 24 0.5 C10 C40 C10 C40 C10 C40 C2 C32 6 C24 14 C16 22 C6 30 10 0.4 C25 C0 C25 C60 C25 C60 C17 C52 C9 C44 C1 C36 7 C26 15 C10 table 32: minimum required time t vac above v ih(ac) (or below v il(ac) ) for valid transition slew rate (v/ns) t v ac (ps) >2.0 175 2.0 170 1.5 167 1.0 163 0.9 162 0.8 161 0.7 159 0.6 155 0.5 150 <0.5 150 576mb: x18, x36 rldram 3 command and address setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 51
figure 22: nominal slew rate and t vac for t is (command and address - clock) v ss setup slew rate rising signal setup slew rate falling signal dtf dtr = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max nominal slew rate v ref to ac region t vac t vac dk dk# ck# ck t is t ih t is t ih nominal slew rate v ref to ac region v ref(dc) - v il(ac)max dtf v ih(ac)min - v ref(dc) dtr note: 1. both the clock and the data strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 command and address setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 52
figure 23: nominal slew rate for t ih (command and address - clock) v ss hold slew rate falling signal hold slew rate rising signal dtr dtf = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max nominal slew rate dc to v ref region dk dk# ck# ck t is t ih t is t ih dc to v ref region nominal slew rate v ref(dc) - v il(dc)max dtr v ih(dc)min - v ref(dc) dtf note: 1. both the clock and the data strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 command and address setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 53
figure 24: tangent line for t is (command and address - clock) v ss setup slew rate rising signal setup slew rate falling signal dtf dtr = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max tangent line v ref to ac region nominal line t vac t vac dk dk# ck# ck t is t ih t is t ih v ref to ac region tangent line nominal line tangent line v ih(dc)min - v ref(dc) dtr ] [ tangent line v ref(dc) - v il(ac)max dtf ] [ note: 1. both the clock and the data strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 command and address setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 54
figure 25: tangent line for t ih (command and address - clock) v ss d tr v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max tangen t line dc to v ref region dk dk# ck# ck t is t ih t is t ih dc to v ref region tangen t line nominal line nominal line dt f hold slew rate rising signal = tangent line v ref(dc) - v il(dc)max dtr ] [ hold slew rate falling signal = tangent line v ih(dc)min - v ref(dc) dtf ] [ note: 1. both the clock and the data strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 command and address setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 55
data setup, hold, and derating the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet t ds (base) and t dh (base) v alues (see the table belo w; values come from table 27 (page 43)) to the t ds and t dh derating values (see table 34 (page 57)), respectively. example: t ds (total setup time) = t ds (base) + t ds. for a valid transition, the input sig- nal has to remain above/below v ih(ac) /v il(ac) for some time t vac (see table 35 (page 57)). although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached v ih(ac) /v il(ac) ) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach v ih / v il(ac) . for slew rates which fall between the values listed in table 34 (page 57) and table 35 (page 57), the derating values may obtained by linear interpolation. setup ( t ds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup ( t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between the shaded v ref(dc) -to-ac region, use the nominal slew rate for derating value (see figure 26 (page 58)). if the actual signal is later than the nominal slew rate line anywhere between the shaded v ref(dc) -to-ac region, the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for derating value (see figure 28 (page 60)). hold ( t dh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . hold ( t dh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between the shaded dc-to-v ref(dc) region, use the nominal slew rate for derating value (see figure 27 (page 59)). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded dc-to-v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc-to-v ref(dc) region is used for derating val- ue (see figure 29 (page 61)). table 33: data setup and hold values at 1 v/ns (dkx, dkx# at 2v/ns) C ac/dc-based symbol rl3-2133 rl3-1866 rl3-1600 units reference t ds(base),ac150 C30 -15 10 ps v ih(ac) /v il(ac) t dh(base),dc100 5 20 45 ps v ih(dc) /v il(dc) 576mb: x18, x36 rldram 3 data setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 56
table 34: derating values for t ds/ t dh C ac150/dc100-based empty cells indicate slew rate combinations not supported t ds, t dh derating (ps) - ac/dc-based dq slew rate (v/ns) dkx, dkx# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 75 50 75 50 75 50 1.5 50 34 50 34 50 34 58 42 1.0 0 0 0 0 0 0 8 8 16 16 0.9 0 C4 0 C4 8 4 16 12 24 20 0.8 0 C10 8 C2 16 6 24 14 32 24 0.7 8 C8 16 0 24 8 32 18 40 34 0.6 15 C10 23 C2 31 8 39 24 0.5 14 C16 22 C6 30 10 0.4 7 C26 15 C10 table 35: minimum required time t vac above v ih(ac) (or below v il(ac) ) for valid transition slew rate (v/ns) t v ac (ps) >2.0 175 2.0 170 1.5 167 1.0 163 0.9 162 0.8 161 0.7 159 0.6 155 0.5 150 <0.5 150 576mb: x18, x36 rldram 3 data setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 57
figure 26: nominal slew rate and t vac for t ds (dq - strobe) v ss setup slew rate rising signal setup slew rate falling signal dtf dtr = = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max nominal slew rate v ref to ac region t vac t vac t dh t ds dk dk# t dh t ds ck# ck v ref to ac region nominal slew rate v ih(ac)min - v ref(dc) dtr v ref(dc) - v il(ac)max dtf note: 1. both the clock and the strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 data setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 58
figure 27: nominal slew rate for t dh (dq - strobe) v ss hold slew rate rising signal dtr dtf = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max nominal slew rate dc to v ref region t dh t ds dk dk# t dh t ds ck# ck dc to v ref region nominal slew rate v ref(dc) - v il(dc)max dtr hold slew rate falling signal = v ih(dc)min - v ref(dc) dtf note: 1. both the clock and the strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 data setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 59
figure 28: tangent line for t ds (dq - strobe) v ss setup slew rate rising signal dtf dtr = v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max tangent line v ref to ac region nominal line t vac t vac t dh t ds dk dk# t dh t ds ck# ck v ref to ac region tangent line nominal line dtr tangent line v ih(ac)min - v ref(dc) ] [ setup slew rate falling signal = dtf tangent line v ref(dc) - v il(ac)max ] [ note: 1. both the clock and the strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 data setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 60
figure 29: tangent line for t dh (dq - strobe) v ss dtf dtr v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max tangent line dc to v ref region dk dk# ck# ck dc to v ref region tangent line nominal line nominal line t ds t dh t ds t dh hold slew rate rising signal = dtr tangent line v ref(dc) - v il(dc)max ] [ hold slew rate falling signal = dtf tangent line v ih(dc)min - v ref(dc) ] [ note: 1. both the clock and the strobe are drawn on different time scales. 576mb: x18, x36 rldram 3 data setup, hold, and derating integrated silicon solution, inc. ? www.issi.com 01/17/2012 61
commands the following table provides descr iptions of the v alid commands of the rldram 3 de- vice. all command and address inputs must meet setup and hold times with respect to the rising edge of ck. table 36: command descriptions command description nop the nop command prevents new commands from being executed by the dram. operations already in progress are not af fected by nop commands. output values depend on com- mand history . mrs mode registers mr0, mr1, and mr2 are used to define various modes of programmable operations of the dram. a mode register is programmed via the mode register set (mrs) command during initi- alization and retains the stored information until it is reprogrammed, reset# goes low , or until the device loses power . the mrs command can be issued only when all banks are idle, and no bursts are in progress. read the read command is used to initiate a burst read access to a bank. the ba[3:0] inputs select a bank, and the address provided on inputs a[19:0] select a specific location within a bank. write the write command is used to initiate a burst write access to a bank (or banks). mrs bits mr2[4:3] select single, dual, or quad bank write protocol. the ba[ x:0] inputs select the bank(s) (x = 3, 2, or 1 for single, dual, or quad bank write, respectively). the address provided on inputs a[19:0] select a specific location within the bank. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if the dm signal is registered low , the corresponding data will be written to memory. if the dm signal is registered high, the cor- responding data inputs will be ignored (that is, this part of the data word will not be written). aref the aref command is used during normal operation of the rldram 3 to refresh the memory con- tent of a bank. there are two methods by which the rldram 3 can be refreshed, both of which are selected within the mode register. the first method, bank address-controlled aref , is identical to the method used in rldram2. the second method, multibank aref, enables refreshing of up to four banks simultaneously. more info is available in the auto refresh section. for both methods, the com- mand is nonpersistent, so it must be issued each time a refresh is required. table 37: command table note 1 applies to the entire table operation code cs# we# ref# a[19:0] ba[3:0] notes nop nop h x x x x mrs mrs l l l opcode opcode read read l h h a ba 2 write write l l h a ba 2 auto refresh aref l h l a ba 3 notes: 1. x = dont care; h = logic high; l = logic low ; a = valid address; ba = valid bank ad- dress; opcode = mode register bits 2. address width varies with burst length and configuration; see the address widths of dif ferent burst lengths table for more information. 3. bank address signals (ba) are used only during bank address-controlled aref; address signals (a) are used only during multibank aref. 576mb: x18, x36 rldram 3 commands integrated silicon solution, inc. ? www.issi.com 01/17/2012 62
mode register set (mrs) command the mode registers, mr0, mr1, and mr2, store the data for contr olling the oper ating modes of the memory. the mode register set (mrs) command programs the rldram 3 operating modes and i/o options. during an mrs command, the address inputs are sampled and stored in the mode registers. the ba[1:0] signals select between mode registers 0C2 (mr0Cmr2). after the mrs command is issued, each mode register retains the stored information until it is reprogrammed, until reset# goes low, or un- til the device loses power. after issuing a valid mrs command, t mrsc must be met before any command can be issued to the rldram 3. the mrs command can be issued only when all banks are idle, and no bursts are in progress. figure 30: mrs command protocol dont care ck ck# cs# we# ref# opcode opcode address bank address 576mb: x18, x36 rldram 3 mode register set (mrs) command integrated silicon solution, inc. ? www.issi.com 01/17/2012 63
mode register 0 (mr0) figure 31: mr0 definition for non-multiplexed address mode a6a7 a4 a8a9a10 a3 a2 a1 a0 a5 address bus ...a17ba0ba1ba2ba3 t rc_mrs dllam 0 1 0 1 reserved mrs data latency mode register (mx) 678 9 4 3 2 1 0 5 18192021 17-10 m19 0 0 1 1 m18 0 1 0 1 mode register definition mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) reserved m8 0 1 dll enable enable disable m9 0 1 address mux non-multiplexed multiplexed m4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 m7 0 0 0 0 0 0 0 0 data latency (rl & wl) rl = 3 ; wl = 4 rl = 4 ; wl = 5 rl = 5 ; wl = 6 rl = 6 ; wl = 7 rl = 7 ; wl = 8 rl = 8 ; wl = 9 rl = 9 ; wl = 10 rl = 10 ; wl = 11 rl = 11 ; wl = 12 rl = 12 ; wl = 13 rl = 13 ; wl = 14 rl = 14 ; wl = 15 rl = 15 ; wl = 16 rl = 16 ; wl = 17 reserved reserved m0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 m3 0 0 0 0 0 0 0 0 t rc_mrs 2 2,3 3 2 4 2 5 6 7 8 9 10 11 12 reserved reserved reserved reserved reserved notes: 1. ba2, ba3, and all address balls corresponding to reserved bits must be held low during the mrs command. 2. bl8 not allowed. 3. bl4 not allowed. 576mb: x18, x36 rldram 3 mode register 0 (mr0) integrated silicon solution, inc. ? www.issi.com 01/17/2012 64
t rc bits mr0[3:0] select the number of clock cycles requir ed to satisfy the t r c specifications. after a read, write, or aref command is issued to a bank, a subsequent read, write, or aref cannot be issued to the same bank until t rc has been satisfied. the correct value (trc_mrs) to program into mr0[3:0] is shown in the table below. table 38: trc_mrs mr0[3:0] values parameter -093e -093 -107e -107 -125e -125 rl=3; wl=4 trc_mrs 2 2 reserved reserved reserved reserved rl=4; wl=5 trc_mrs 2 3 2 3 3 3 rl=5; wl=6 trc_mrs 3 4 3 3 3 3 rl=6; wl=7 trc_mrs 4 4 3 4 4 4 rl=7; wl=8 trc_mrs 4 4 4 4 4 4 rl=8; wl=9 trc_mrs 5 6 4 5 5 5 rl=9; wl=10 trc_mrs 5 6 5 6 6 6 rl=10; wl=11 trc_mrs 6 7 5 6 6 6 rl=11; wl=12 trc_mrs 6 7 6 7 7 7 rl=12; wl=13 trc_mrs 7 8 6 7 7 7 rl=13; wl=14 trc_mrs 7 8 7 8 8 8 rl=14; wl=15 trc_mrs 8 10 7 8 reserved 9 rl=15; wl=16 trc_mrs 8 10 8 10 reserved 10 rl=16; wl=17 trc_mrs 9 11 reserved reserved reserved 10 data latency the data latency register uses mr0[7:4] to set both the read and write latency (rl and wl). the v alid operating frequencies for each data latency register setting can be found in table 27 (page 43). dll enable/disable through the programming of mr0[8], the dll can be enabled or disabled. the dll must be enabled for normal operation. the dll must be enabled during the initialization routine and upon returning to normal operation after having been disa- bled for the purpose of debugging or evaluation. to operate the rldram with the dll disabled, the t rc mrs setting must equal the read latency (rl) setting. enabling the dll should always be followed by resetting the dll using the appropriate mr1 com- mand. address multiplexing although the rldram has the ability to operate similar to an sram interface by ac- cepting the entire address in one clock (non-multiplexed, or broadside addressing), mr0[9] can be set to 1 so that it functions with multiplexed addressing, similar to a tra- ditional dram. in multiplexed address mode, the address is provided to the rldram in two parts that are latched into the memory with two consecutive rising edges of ck. 576mb: x18, x36 rldram 3 mode register 0 (mr0) integrated silicon solution, inc. ? www.issi.com 01/17/2012 65
when in multiplexed address mode, only 11 address balls are required to control the rldram, as opposed to 20 address balls when in non-multiplexed address mode. the data bus efficiency in continuous burst mode is only affected when using the bl = 2 set- ting because the device r equires two clocks to read and write data. during multiplexed mode, the bank addresses as well as write and read commands are issued during the first address part, a x . the address mapping in multiplexed address mode table shows the addresses needed for both the first and second rising clock edges (a x and ay , re- spectively). after mr0[9] is set high, read, write, and mrs commands follow the format descri- bed in the command description in multiplexed address mode figure. refer to multi- plexed address mode for further information on operation with multiplexed address- ing. 576mb: x18, x36 rldram 3 mode register 0 (mr0) integrated silicon solution, inc. ? www.issi.com 01/17/2012 66
mode register 1 (mr1) figure 32: mr1 definition for non-multiplexed address mode a0a1a2a3a4a5a6 a7 a8 a17 ... a11 a9 a10 ba0ba1ba2ba3 address bus odt reserved mrs drive mode register (mx) dll refbl zqzqe 18 0 1 0 1 19 20 21 45678910 17-11 3 2 1 0 m0 0 1 0 1 m1 0 0 1 1 output drive rzq/6 (40w) rzq/4 (60w) reserved reserved m9 0 1 0 1 m10 0 0 1 1 burst length 2 4 8 reserved zq calibration selection short zq calibration long zq calibration m2 0 1 0 1 0 1 0 1 odt of f rzq/6 (40w) rzq/4 (60w) rzq/2 (120w) reserved reserved reserved reserved m3 0 0 1 1 0 0 1 1 1 1 1 1 m4 0 0 0 0 m19 0 0 1 1 m18 0 1 0 1 mode register definition mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) reserved dll reset no yes m8 0 1 aref p rotocol bank address control multibank m7 0 1 m6 0 1 m5 0 1 zq calibration enable disabled - default enable notes: 1. ba2, ba3, and all address balls corresponding to reserved bits must be held low during the mrs command. 2. bl8 not available in x36. output drive impedance the rldram 3 uses pr ogr ammable impedance output buffers , which enable the user to match the driver impedance to the system. mr1[0] and mr1[1] are used to select 40 5 or 605 output impedance, but the device powers up with an output impedance of 405. the drivers have symmetrical output impedance. to calibrate the impedance a 240 5 1% external precision resistor (rzq) is connected between the zq ball and v ssq . the output impedance is calibrated during initialization through the zqcl mode regis- ter setting. subsequent periodic calibrations (zqcs) may be performed to compensate for shifts in output impedance due to changes in temperature and voltage. more de- tailed information on calibration can be found in the zq calibration section. dq on-die termination (odt) mr1[4:2] are used to select the value of the on-die termination (odt) for the dq, dk x and dm balls. when enabled, odt terminates these balls to v ddq /2. the rldram 3 device supports 40 5, 60, or 1205 odt. the odt function is dynamically switched off when a dq begins to drive after a read command has been issued. similarly, odt is designed to switch on at the dqs after the rldram has issued the last piece of data. the dm and dkx balls are always terminated after odt is enabled. dll reset programming mr1[5] to 1 activates the dll reset function. mr1[5] is self-clearing, meaning it returns to a value of 0 after the dll reset function has been initiated. 576mb: x18, x36 rldram 3 mode register 1 (mr1) integrated silicon solution, inc. ? www.issi.com 01/17/2012 67
whenever the dll reset function is initiated, ck/ck# must be held stable for 512 clock cycles before a read command can be issued. this is to allo w time for the inter - nal clock to be synchronized with the external clock. failing to wait for synchronization to occur may cause output timing specifications, such as t ckqk, to be invalid . zq calibration the zq calibration mode register command is used to calibrate the dram output drivers (r on ) and odt values (r tt ) over process, voltage, and temperature, provided a dedicated 240? (1%) external resistor is connected from the drams rzq ball to v ssq . bit mr1[6] selects between zq calibration long (zqcl) and zq calibration short (zqcs), each of which are described in detail below. when bit mr1[7] is set high, it enables the calibration sequence. upon completion of the zq calibration sequence, mr1[7] automatically resets low. the rldram 3 needs a longer time to calibrate r on and odt at power-up initialization and a relatively shorter time to perform periodic calibrations. an example of zq calibra- tion timing is shown below. all banks must have t rc met before zqcl or zqcs mode register settings can be issued to the dram. no other activities (other than loading another zqcl or zqcs mode reg- ister setting may be issued to another dram) can be performed on the dram channel by the controller for the duration of t zqinit or t zqoper. the quiet time on the dram channel helps accurately calibrate r on and odt. after dram calibration is achieved, the dram will disable the zq balls current consumption path to reduce power. zq calibration mode register settings can be loaded in parallel to dll reset and locking time. in systems that share the zq resistor between devices, the controller must not allow overlap of t zqinit, t zqoper, or t zqcs between devices. 576mb: x18, x36 rldram 3 mode register 1 (mr1) integrated silicon solution, inc. ? www.issi.com 01/17/2012 68
figure 33: zq calibration timing (zqcl and zqcs) nop mrs nop nop valid valid mrs nop nop nop valid command indicates a break in time scale t0 t1 ta0 ta1 ta2 ta3 tb0 tb1 tc0 tc1 tc2 address valid valid valid ck ck# dont care or unknown dq qvld activities activ- ities qk# qk t zqcs t zq init or t zq oper activities activ- ities zqcl zqcs notes: 1. all devices connected to the dq bus should be held high-z during calibration. 2. the state of qk and qk# are unknown during zq calibration. 3. t mrsc after loading the mr1 settings, qvld output drive strength will be at the value selected or lower until zq calibration is complete. zq calibration long the zq calibration long (z qcl) mode register setting is used to perform the initial cali- bration during a power-up initialization and reset sequence. it may be loaded at any time by the controller depending on the system environment. zqcl triggers the cali- bration engine inside the dram. after calibration is achieved, the calibrated values are transferred from the calibration engine to the dram i/o, which are reflected as upda- ted r on and odt values. the dram is allowed a timing window defined by either t zqinit or t zqoper to perform the full calibration and transfer of values. when zqcl is issued during the initialization sequence, the timing parameter t zqinit must be satisfied. when initialization is com- plete, subsequent loading of the zqcl mode register setting requires the timing param- eter t zqoper to be satisfied. zq calibration short the zq calibration short (zqcs) mode register setting is used to perform periodic cali- brations to account for small voltage and temperature variations. the shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter t zqcs. zqcs can effectively correct a minimum of 0.5% r on and r tt impedance error within 64 clock cycles, assuming the maximum sensitivities speci- fied in the odt temperature and voltage sensitivity and the output driver voltage and temperature sensitivity tables. 576mb: x18, x36 rldram 3 mode register 1 (mr1) integrated silicon solution, inc. ? www.issi.com 01/17/2012 69
auto refresh protocol the auto refresh (aref) protocol is selected with bit mr1[8]. ther e are two ways in which aref commands can be issued to the rldram. depending upon how bit mr1[8] is programmed, the memory controller can issue either bank address-control- led or multibank aref commands. bank address-controlled aref uses the ba[3:0] in- puts to refresh a single bank per command. multibank aref is enabled by setting bit mr1[8] high during an mrs command. this refresh protocol enables the simultane- ous refreshing of a row in up to four banks. in this method, the address pins a[15:0] rep- resent banks 0C15, respectively. more information on both aref protocols can be found in auto refresh command (page 77). burst length (bl) burst length is defined by mr1[9] and mr1[10]. read and write accesses to the rldram are burst-oriented, with the burst length being programmable to 2, 4, or 8. figure 34 (page 71) shows the different burst lengths with respect to a read com- mand. changes in the burst length affect the width of the address bus (see the following table for details). the data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed. table 39: address widths of different burst lengths burst length configuration x18 x36 2 a[19:0] a[18:0] 4 a[18:0] a[17:0] 8 a[17:0] na 576mb: x18, x36 rldram 3 mode register 1 (mr1) integrated silicon solution, inc. ? www.issi.com 01/17/2012 70
figure 34: read burst lengths command address dq qvld do an qk qk# qk qk# qk qk# rl = 4 ck ck# dq do an dont care transitioning data dq do an read nop nop nop nop nop nop nop bank a, col n t0 t1 t2 t3 t4n t5n t4 t5 t6n t7n t6 t7 qvld qvld bl = 2 bl = 4 bl = 8 nop note: 1. do a n = data-out from bank a and address an. 576mb: x18, x36 rldram 3 mode register 1 (mr1) integrated silicon solution, inc. ? www.issi.com 01/17/2012 71
mode register 2 (mr2) figure 35: mr2 definition for non-multiplexed address mode a0a1a2a3a4...a17ba0ba1ba2ba3 address bus rtren write reserved mrs mode register (mx) 17-5 1819 0 1 0 1 2021 234 1 0 m4 0 0 1 1 m3 0 1 0 1 write protocol single bank dual bank quad bank reserved read training register enable normal rldram operation read training enabled m19 0 0 1 1 m18 0 1 0 1 mode register definition mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) reserved m2 0 1 m1 0 0 1 1 m0 0 1 0 1 read training register 0-1-0-1 on all dqs even dqs: 0-1-0-1 ; odd dqs: 1-0-1-0 reserved reserved note: 1. ba2, ba3, and all address balls corresponding to reserved bits must be held low during the mrs command. read training register (rtr) the read tr aining r egister (rtr) is controlled through mr2[2:0]. it is used to output a predefined bit sequence on the output balls to aid in system timing calibration. mr2[2] is the master bit that enables or disables access to the read training register, and mr2[1:0] determine which predefined pattern for system calibration is selected. if mr2[2] is set to 0, the rtr is disabled, and the dram operates in normal mode. when mr2[2] is set to 1, the dram no longer outputs normal read data, but a predefined pat- tern that is defined by mr2[1:0]. prior to enabling the rtr, all banks must be in the idle state ( t rc met). when the rtr is enabled, all subsequent read commands will output four bits of a predefined se- quence from the rtr on all dqs. the read latency during rtr is defined with the data latency bits in mr0. to loop on the predefined pattern when the rtr is enabled, suc- cessive read commands must be issued and satisfy t rtrs. address balls a[19:0] are considered "don't care" during rtr read commands. bank address bits ba[3:0] must access bank 0 with each rtr read command. t rc does not need to be met in between rtr read commands to bank 0. when the rtr is enabled, only read commands are allowed. when the last rtr read burst has completed and t rtre has been satisfied, an mrs command can be issued to exit the rtr. standard rldram 3 operation may then start after t mrsc has been met. the reset function is supported when the rtr is ena- bled. if mr2[1:0] is set to 00 a 0-1-0-1 pattern will be output on all dqs with each rtr read command. if mr2[1:0] is set to 01, a 0-1-0-1 pattern will output on all even dqs and the opposite pattern, a 1-0-1-0, will output on all odd dqs with each rtr read command. note: enabling rtr may corrupt previously written data. 576mb: x18, x36 rldram 3 mode register 2 (mr2) integrated silicon solution, inc. ? www.issi.com 01/17/2012 72
figure 36: read training function - back-to-back readout ck ck# command bank qvld dq read mrs mr2[21:18] t0 t1 t2 dont care indicates a break in time scale transitioning data nop nop read t3 t4 t5 bank 0 bank 0 bank 0 bank 0 bank 0 t6 read t7 t8 t9 t10 t11 t12 t13 nop nop dk dk# qk dm qk# rl nop read t mrsc t rtrs t rtrs t rtrs t rtrs read nop nop mrs mr2[21:18] mr2[17:0] valid ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) address mr2[17:0] ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rtre t mrsc note: 1. rl = read latency defined with data latency mr0 setting. draft 12/19/2011 576mb: x18, x36 rldram 3 mode register 2 (mr2) integrated silicon solution, inc. ? www.issi.com 01/17/2012 73
write protocol single or multibank write operation is pr ogr ammed with bits mr2[4:3]. the purpose of multibank write operation is to reduce the effective t rc during read commands. when dual- or quad-bank write protocol is selected, identical data is written to two or four banks, respectively. with the same data stored in multiple banks on the rldram, the memory controller can select the appropriate bank to read the data from and min- imize t rc delay. detailed information on the multibank write protocol can be found in multibank write (page 75). write command write accesses are initiated with a write command. the address needs to be provided concurrent with the write command. during write commands, data will be registered at both edges of dk, according to the programmed burst length (bl). the rldram operates with a write latency (wl) de- termined by the data latency bits within mr0. the first valid data is registered at the first rising dk edge wl cycles after the write command. any write burst may be followed by a subsequent read command (assuming t rc is met). depending on the amount of input timing skew, an additional nop command might be necessary between write and read commands to avoid external data bus contention (see figure 44 (page 83)). setup and hold times for incoming dq relative to the dk edges are specified as t ds and t dh. the input data is masked if the corresponding dm signal is high. figure 37: write command ck# ck we# ref# cs# a address bank address ba dont care 576mb: x18, x36 rldram 3 write command integrated silicon solution, inc. ? www.issi.com 01/17/2012 74
multibank write all the information provided abo v e in the write section is applicable to a multibank write operation as well. either two or four banks can be simultaneously written to when the appropriate mr2[4:3] mode register bits are selected. if a dual-bank write has been selected through the mode register, both banks x and x +8 will be written to simultaneously with identical data provided during the write command. for example, when a dual-bank write has been loaded and the bank ad- dress for bank 1 has been provided during the write command, bank 9 will also be written to at the same time. when a dual-bank write command is issued, only bank address bits ba[2:0] are valid and ba3 is considered a dont care. the same methodology is used if the quad-bank write has been selected through the mode register. under these conditions, when a write command is issued to bank x, the data provided on the dqs will be issued to banks x, x+4, x+8, and x +12. when a quad-bank write command is issued, only bank address bits ba[1:0] are valid and ba[3:2] are considered dont care. the timing parameter t saw must be adhered to when operating with multibank write commands. this parameter limits the number of active banks at 16 within an 8ns win- dow. the t mmd specification must also be followed if the quad-bank write is being used. this specification requires two clock cycles between any bank command (read, write, or aref) to a quad-bank write or a quad-bank write to any bank command. the data bus efficiency is not compromised if bl4 or bl8 is being utilized. read command read accesses are initiated with a read command (see the figure below). addresses are provided with the read command. during read bursts, the memory device drives the read data so it is edge-aligned with the qk signals. after a programmable read latency, data is available at the outputs. one half clock cycle prior to valid data on the read bus, the data valid signal(s), qvld, transitions from low to high. qvld is also edge-aligned with the qk signals. the skew between qk and the crossing point of ck is specified as t ckqk. t qkq x is the skew between a qk pair and the last valid data edge generated at the dq signals in the associated byte group, such as dq[7:0] and qk0. t qkq x is derived at each qk clock edge and is not cumulative over time. for the x36 device, the t qkq02 and t qkq13 specifica- tions define the relationship between the dqs and qk signals within specific data word groupings. t qkq02 defines the skew between qk0 and dq[26:18] and between qk2 and dq[8:0]. t qkq13 defines the skew between qk1 and dq[35:17] and between qk3 and dq[17:9]. after completion of a burst, assuming no other commands have been initiated, output data (dq) will go high-z. the qvld signal transitions low on the last bit of the read burst. the qk clocks are free-running and will continue to cycle after the read burst is complete. back-to-back read commands are possible, producing a continuous flow of output data. any read burst may be followed by a subsequent write command. some systems having long line lengths or severe skews may need an additional idle cycle inserted be- tween read and write commands to prevent data bus contention. 576mb: x18, x36 rldram 3 read command integrated silicon solution, inc. ? www.issi.com 01/17/2012 75
figure 38: read command dont care ck ck# cs# we# ref# a ba address bank address 576mb: x18, x36 rldram 3 read command integrated silicon solution, inc. ? www.issi.com 01/17/2012 76
auto refresh command the rldram 3 device uses two unique auto refresh (aref) command protocols , bank addr ess-controlled aref and multibank aref. the desired protocol is selected by setting mr1[8] low (for bank address-controlled aref) or high (for multibank aref) during an mrs command. bank address-controlled aref is identical to the method used in rldram2 devices, whereby banks are refreshed independently. the value on bank addresses ba[3:0], issued concurrently with the aref command, define which bank is to be refreshed. the array address is generated by an internal refresh counter, effectively making each address bit a "don't care" during the aref command. the de- lay between the aref command and a subsequent command to the same bank must be at least t rc. figure 39: bank address-controlled auto refresh command ck# ck we# ref# cs# address bank address ba[3:0] dont care the multibank aref protocol, enabled by setting bit mr1[8] high during an mrs command, enables the simultaneous refresh of a ro w in up to four banks . in this meth- od, address balls a[15:0] represent banks [15:0], respectively. the row addresses are gen- erated by an internal refresh counter for each bank; therefore, the purpose of the ad- dress balls during an aref command is only to identify the banks to be refreshed. the bank address balls ba[3:0] are considered "don't care" during a multibank aref com- mand. a multibank auto refresh is performed for a given bank when its corresponding ad- dress ball is asserted high during an aref command. any combination of up to four address balls can be asserted high during the rising clock edge of an aref command to simultaneously refresh a row in each corresponding bank. the delay between an aref command and subsequent commands to the banks refreshed must be at least t rc. adherence to t saw must be followed when simultaneously refreshing multiple banks. if refreshing three or four banks with the multibank aref command, t mmd must be followed. this specification requires two clock cycles between any bank com- mand (read, write, aref) to the multibank aref or the multibank aref to any bank 576mb: x18, x36 rldram 3 auto refresh command integrated silicon solution, inc. ? www.issi.com 01/17/2012 77
command. note that refreshing one or two banks with the multibank aref command is not subject to the t mmd specification. the entire device must be refreshed ev er y 64ms ( t ref). the rldram device requires 128k cycles at an average periodic interval of 0.489s max (64ms/[8k rows x 16 banks]). figure 40: multibank auto refresh command ck# ck we# ref# cs# address bank address a[15:0] dont care 576mb: x18, x36 rldram 3 auto refresh command integrated silicon solution, inc. ? www.issi.com 01/17/2012 78
initialization operation the rldram 3 device must be powered up and initializ ed in a pr edefined manner. op- erational procedures other than those specified may result in undefined operations or permanent damage to the device. the following sequence is used for power-up: 1. apply power (v ext , v dd , v ddq ). apply v dd and v ext before, or at the same time as, v ddq . v dd must not exceed v ext during power supply ramp. v ext , v dd , v ddq must all ramp to their respective minimum dc levels within 200ms. 2. ensure that reset# is below 0.2 v ddq during power ramp to ensure the outputs remain disabled (high-z) and odt is off (r tt is also high-z). dqs, and qk signals will remain high-z until mr0 command. all other inputs may be undefined dur- ing the power ramp. 3. after the power is stable, reset# must be low for at least 200s to begin the initi- alization process. 4. after 100 or more stable input clock cycles with nop commands, bring reset# high. 5. after reset# goes high, a stable clock must be applied in conjunction with nop commands for 10,000 cycles. 6. load desired settings into mr0. 7. t mrsc after loading the mr0 settings, load operating parameters in mr1, includ- ing dll reset and long zq calibration. 8. after the dll is reset and long zq calibration is enabled, the input clock must be stable for 512 clock cycles while nops are issued. 9. load desired settings into mr2. if using the rtr, follow the procedure outlined in the read training function C back-to-back readout figure prior to entering nor- mal operation. 10. the rldram 3 is ready for normal operation. 576mb: x18, x36 rldram 3 initialization operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 79
figure 41: power-up/initialization sequence dm address ck ck# dk dk# t cl command nop t ch t ck t dkl t dkh t dk 100 cycles dq qvld 1 v ext v ref v ddq v dd reset# stable and valid clock power-up ramp t (max) = 200ms qk qk# see power-up conditions in the initialization sequence text = 20ns t ioz r tt t = 200s (min) read training register specs apply t mrsc 512 clock cycles for dll reset & zq calibration 10,000 ck cycles (min) mr1 mr2 mr0 valid all voltage supplies valid and stable nop nop valid mrs mrs mrs dont care or unknown normal operation indicates a break in time scale notes: 1. qvld output drive status during power-up and initialization: a. qvld remains high-z until 20ns after power supplies are stable and tck or ck have cycled 4 times. b. qvld will then drive low with 40 or lower until the output drive value selected in mr1 is enabled. 576mb: x18, x36 rldram 3 initialization operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 80
c. t mrsc after loading the mr1 settings, qvld output drive strength will be at the value selected or lower until zq calibration is complete. d. qvld will meet the output drive strength specifications upon completion of the zq calibration timing. 2. after mr2 has been issued, rtt is either high-z or enabled to the odt value selected in mr1. 576mb: x18, x36 rldram 3 initialization operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 81
write operation figure 42: write burst t ckdknom command write nop nop nop nop nop address bank a, add n nop ck ck# t0 t1 t2 t3 t4 t5 t5n t6 t6n t7 dk dk# dq dm di an t ckdkmin dq dm di an t ckdkmax dq dm di an dont care transitioning data wl = 5 dk dk# dk dk# nop wl - t ckdk wl + t ckdk note: 1. di an = data-in for bank a and address n. 576mb: x18, x36 rldram 3 write operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 82
figure 43: consecutive write bursts ck ck# command write nop write write nop nop nop nop nop bank a, add n bank b, add n bank a, add n nop address t0 t1 t2 t3 t4 t5 t6 t6n t5n t7 t8 t9 t8n t7n dq dm di bn di an di an dont care transitioning data wl t rc wl dk dk# indicates a break in time scale note: 1. di an (or bn or cn) = data-in for bank a (or b or c) and address n. figure 44: write-to-read command nop read nop nop nop address bank a, add n nop ck ck# t0 t1 t2 t3 t4 t5 t5n t6 t6n t7 dq dm di an do bn dont care transitioning data wl = 5 qvld dk# dk qk# qk nop bank b, add n write rl = 4 notes: 1. di an = data-in for bank a and address n. 2. do bn = data-out from bank b and address n. 576mb: x18, x36 rldram 3 write operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 83
figure 45: write - dm operation ck ck# dk dk# t ck t ch t cl t0 t1 t2 t3 t4 t5 t7n t6 t7 t8 t6n nop nop command write bank a, add n nop nop nop nop nop t dkl t dkh dq dm di an t ds t dh dont care transitioning data address wl = 5 nop note: 1. di an = data-in for bank a and address n. 576mb: x18, x36 rldram 3 write operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 84
figure 46: consecutive quad bank write bursts dont care transitioning data command quad-bank write quad-bank write nop nop nop nop address bank a, add n bank b, add n nop ck ck# t0 t1 t2 t3 t4 t5 t5n t6 t6n t7nt7 dq dm di an di bn wl = 5 tmmd = 2 dk dk# nop notes: 1. di an = data-in for bank a, a+4, a+8, and a+12 and address n. 2. di bn = data-in for bank b, b+4, b+8, and b+12 and address n. figure 47: interleaved read and quad bank write bursts dont care transitioning data command read quad-bank write nop read quad-bank write nop address bank a, add n bank b, add n bank c, add n bank d, add n nop ck ck# t0 t1 t2 t3 t4 t5 t5n t6 t6n t7 t8 t8n t9 t9n dq dm do an di bn rl = 5 tmmd = 2 dk qvld dk# qk qk# nop nop nop wl = 6 tmmd = 2 tmmd = 2 notes: 1. do an = data-out for bank a and address n. 2. di bn = data-in for bank b, b+4, b+8, and b+12 and address n. 576mb: x18, x36 rldram 3 write operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 85
read operation figure 48: basic read burst ck ck# t ck t ch t cl t qk t qkh t qkl t rc = 4 rl = 4 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 qk qvld qk# dq t ckqkmin t ckqkmin do an do an nop nop command read bank a add n bank a add n nop nop read nop nop t qk t qkh t qkl dont care transitioning data address qk# qvld qk dq t ckqkmax t ckqkmax t qkvld t qkvld note: 1. do an = data-out from bank a and address an. 576mb: x18, x36 rldram 3 read operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 86
figure 49: consecutive read bursts (bl = 2) command read read read read read read address ck ck# qk qk# qvld dq rl = 4 do an do bn do cn t0 t1 t2 t3 bank a add n bank b add n bank c add n bank d add n bank e add n bank f add n bank g add n read t4n t4 t5 t6 t5n t6n dont care transitioning data note: 1. do an (or bn, cn ) = data-out from bank a (or bank b, c) and address n. figure 50: consecutive read bursts (bl = 4) command read nop read nop read nop address bank a add n bank b add n bank c add n bank d add n ck ck# qk qk# qvld dq rl = 4 do an do bn t0 t1 t2 t3 read t4n t4 t5 t6 t5n t6n dont care transitioning data note: 1. do an (or bn ) = data-out from bank a (or bank b) and address n. 576mb: x18, x36 rldram 3 read operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 87
figure 51: read-to-write ck ck# command address qvld dq read t0 t1 t2 dont care transitioning data nop write t3 t4 t5 nop nop t6 nop wl = 5 t7 t8 nop nop dk dk# qk dm qk# do an di bn rl = 4 bank a, add n bank b, add n nop nop notes: 1. do an = data-out from bank a and address n. 2. di bn = data-in for bank b and address n. figure 52: read data valid window t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 bank, addr n nop read nop nop nop nop nop nop nop nop nop ck ck# command address qvld t qkqx,max qkx, qkx# dq (last data valid) 2 dq (first data no longer valid) 2 all dq collectively 2 do n do n + 3 do n + 2 do n + 1 do n + 7 do n + 6 do n + 5 do n + 4 do n + 2 do n + 1 do n + 7 do n + 6 do n + 5 do n + 4 do n + 3 do n + 2 do n + 1 do n do n + 7 do n + 6 do n + 5 do n do n + 3 dont care transitioning data data valid data valid t qh t qh t hzmax do n + 4 rl = 5 t qkqx,max t lzmin notes: 1. do n = data-out from bank a and address n. 2. represents dqs associated with a specific qk, qk# pair. 3. output timings are referenced to v ddq /2 and dll on and locked. 4. t qkqx defines the skew between the qk0, qk0# pair to its respective dqs. t qkqx does not define the skew between qk and ck. 5. early data transitions may not always happen at the same dq. data transitions of a dq can vary (either early or late) within a burst. 576mb: x18, x36 rldram 3 read operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 88
auto refresh operation figure 53: bank address-controlled auto refresh cycle t0 t1 t2 t3 ck# ck command address bank dq dm dk, dk# dont care ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rc t ck t ch t cl acy acx bay bax arefx arefy indicates a break in time scale notes: 1. aref x (or arefy)= auto refresh command to bank x (or bank y). 2. ac x = any command to bank x; acy = any command to bank y. 3. ba x = bank address to bank x; bay = bank address to bank y. figure 54: multibank auto refresh cycle ck ck# command aref aref address bank bank 0,4,8,12 bank 1,5,9,13 aref dq dm dk, dk# t rc t mmd t0 t1 t2 t3 t4 t5 t6 t7 dont care indicates a break in time scale t mmd bank 2, 3 ac bank 0 576mb: x18, x36 rldram 3 auto refresh operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 89
figure 55: read burst with odt command address dq odt qvld do an odt off qk qk# qk qk# qk qk# rl = 4 ck ck# dq odt odt do an dont care transitioning data dq do an read nop nop nop nop nop nop nop bank a, col n t0 t1 t2 t3 t4n t5n t4 t5 t6n t7n t6 t7 qvld qvld bl = 2 bl = 4 bl = 8 nop odt on odt on odt off odt on on odt off odt on odt on note: 1. do an = data out from bank a and address n. 576mb: x18, x36 rldram 3 auto refresh operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 90
figure 56: read-nop-read with odt command address dq odt qvld do an do bn odt off odt off qk qk# rl = 4 ck ck# dont care transitioning data read nop read nop nop nop nop nop bank a, col n bank b, col n t0 t1 t2 t3 t4n t4 t5 t6n t6 t7 nop odt on odt on odt on note: 1. do an (or bn ) = data-out from bank a (or bank b) and address n. 576mb: x18, x36 rldram 3 auto refresh operation integrated silicon solution, inc. ? www.issi.com 01/17/2012 91
multiplexed address mode figure 57: command description in multiplexed address mode address bank address ax ay ax ay ax ay ay 1 ax 1 mrs aref write read dont care ck# ck cs# we# ref# ba ba ba ba 2 notes: 1. addresses valid only during a multibank auto refresh command. 2. bank addresses valid only during a bank address-controlled auto refresh command. 3. the minimum setup and hold times of the two address parts are defined as t is and t ih. 576mb: x18, x36 rldram 3 multiplexed address mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 92
figure 58: power-up/initialization sequence in multiplexed address mode dm address ck ck# dk t ioz = 20ns dk# t cl command nop t ch t ck t dkl t dkh t dk 100 cycles dq qvld 5 v ext v ref v ddq v dd reset# stable and valid clock power-up ramp t (max) = 200ms qk qk# see power-up conditions in the initialization sequence text r tt high-z t = 200s (min) t mrsc t mrsc 10,000 ck cycles (min) mr0 2 (ax) mr0 (ay) mr0 1 mr1 (ax) all voltage supplies valid and stable nop nop mrs nop mrs mrs mr2 (ax) mr2 (ay) mr1 (ay) valid valid nop mrs nop dont care or unknown indicates a break in time scale 512 clock cycles for dll reset & zq calibration read training register specs apply normal operation notes: 1. set address bit mr0[9] high. this enables the device to enter multiplexed address mode when in non-multiplexed mode operation. multiplexed address mode can also be en- tered at a later time by issuing an mrs command with mr0[9] high. after address bit mr0[9] is set high, t mrsc must be satisfied before the two-cycle multiplexed mode mrs command is issued. 2. address mr0[9] must be set high. this and the following step set the desired mr0 set- ting after the rldram device is in multiplexed address mode. 3. mr1 (a x ), mr1 (ay), mr2 (ax), and mr2 (ay) represent mr1 and mr2 settings in multi- plexed address mode. 4. the above sequence must be followed in order to power up the rldram device in the multiplexed address mode. 5. see qvld output drive strength status during power up and initialization in non-multi- plexed initialization operation section. 6. after mr2 has been issued, r tt is either high-z or enabled to the odt value selected in mr1. 576mb: x18, x36 rldram 3 multiplexed address mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 93
figure 59: mr0 definition for multiplexed address mode t rc_mrs dllam 0 1 0 1 reserved mrs data latency address bus mode register (mx) 678 9 4 3 2 1 0 5 ba0 ba1 ba2ba3 18192021 17-10 m19 0 0 1 1 m18 0 1 0 1 mode register definition mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) reserved m8 0 1 dll enable enable disable m9 0 1 address mux non-multiplexed multiplexed m4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 m7 0 0 0 0 0 0 0 0 data latency (rl & wl) rl = 3 ; wl = 4 rl = 4 ; wl = 5 rl = 5 ; wl = 6 rl = 6 ; wl = 7 rl = 7 ; wl = 8 rl = 8 ; wl = 9 rl = 9 ; wl = 10 rl = 10 ; wl = 11 rl = 11 ; wl = 12 rl = 12 ; wl = 13 rl = 13 ; wl = 14 rl = 14 ; wl = 15 rl = 15 ; wl = 16 rl = 16 ; wl = 17 reserved reserved a3 a4 a8a9 ay a18.......a10 a18.......a10 a8a9 a0 a4 a3 a5 ax m0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 m3 0 0 0 0 0 0 0 0 t rc_mrs 2 2,3 3 2 4 2 5 6 7 8 9 10 11 12 reserved reserved reserved reserved reserved notes: 1. ba2, ba3, and all address balls corresponding to reserved bits must be held low during the mrs command. 2. bl8 not allowed. 3. bl4 not allowed. 576mb: x18, x36 rldram 3 multiplexed addr ess mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 94
figure 60: mr1 definition for multiplexed address mode odt reserved mrs drive mode register (mx) dll refbl 2 zqzqe 18 0 1 0 1 19 20 21 45678910 17-11 3 2 1 0 m0 0 1 0 1 m1 0 0 1 1 output drive rzq/6 (40 w) rzq/4 (60 w) reserved reserved m9 0 1 0 1 m10 0 0 1 1 burst length 2 4 8 reserved zq calibration selection short zq calibration long zq calibration m2 0 1 0 1 0 1 0 1 odt of f rzq/6 (40w) rzq/4 (60w) rzq/2 (120w) reserved reserved reserved reserved m3 0 0 1 1 0 0 1 1 1 1 1 1 m4 0 0 0 0 m19 0 0 1 1 m18 0 1 0 1 mode register definition mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) reserved ba0ba1ba2ba3 dll reset no yes m8 0 1 aref protocol bank address control multibank m7 0 1 m6 0 1 m5 0 1 zq calibration enable disabled - default enable address bus a3a4 a9 a18.......a13 a18.......a13 a0 a3a4a5 a8 ay ax a9 a8 a10 notes: 1. ba2, ba3, and all address balls corresponding to reserved bits must be held low during the mrs command. 2. bl8 not available in x36. 576mb: x18, x36 rldram 3 multiplexed addr ess mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 95
figure 61: mr2 definition for multiplexed address mode rtren write reserved mrs mode register (mx) 17-5 1819 0 1 0 1 2021 234 1 0 m1 0 0 1 1 m0 0 1 0 1 read training register 0-1-0-1 on all dqs even dqs: 0-1-0-1 ; odd dqs: 1-0-1-0 reserved reserved m4 0 0 1 1 m3 0 1 0 1 write protocol single bank dual bank quad bank reserved read training register enable normal rldram operation read training enabled m19 0 0 1 1 m18 0 1 0 1 mode register definition mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) reserved ba0ba1ba2ba3 m2 0 1 address bus a3a4 ay a18.......a5 a18.......a5 a0 ax a4 a3 note: 1. ba2, ba3, and all address balls corresponding to reserved bits must be held low during the mrs command. table 40: address mapping in multiplexed addr ess mode data width burst length ball address a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 x36 2 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 4 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 x ay x a1 a2 x a6 a7 x a11 a12 a16 a15 x18 2 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 4 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 8 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 x ay x a1 a2 x a6 a7 x a11 a12 a16 a15 note: 1. x = dont care 576mb: x18, x36 rldram 3 multiplexed address mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 96
data latency in multiplexed address mode when in multiplexed address mode, data latency (read and write) begins when the a y part of the address is issued with any read or write command. t rc is measured from the clock edge in which the command and a x part of the address is issued in both multiplexed and non-multiplexed address mode. refresh command in multiplexed address mode similar to other commands when in multiplexed address mode, both modes of aref (single and multibank) are executed on the rising clock edge, following the one on which the command is issued. however, when in bank address-controlled aref, as only the bank address is required, the next command can be applied on the following clock. when using multibank aref, the bank addresses are mapped across a x and ay so a sub- sequent command cannot be issued until two clock cycles later. figure 62: bank address-controlled auto refresh operation with multiplexed addressing ck ck# command ac 1 nop ay aref aref aref aref aref aref aref aref ac 1 bank bank 0 bank n bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank n address ax ay ax t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 dont care note: 1. any command subject to t rc specification. figure 63: multibank auto refresh operation with multiplexed addressing ck ck# command aref 1 nop ay aref 1 aref 1 nop nop ac 2 nop bank address ax ay ax ay ax ay ax bank n t0 t1 t2 t3 t4 t5 t6 t7 dont care notes: 1. usage of multibank aref subject to t saw and t mmd specifications. 2. any command subject to t rc specification. 576mb: x18, x36 rldram 3 multiplexed address mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 97
figure 64: consecutive write bursts with multiplexed addressing ck ck# command write nop ay write write nop nop nop nop nop bank bank a ay nop bank b bank a address ax ax ax ay t0 t1 t2 t3 t4 t5 t6 t6n t7 t8 t9 t8n t7n dq dm di b di a dont care transitioning data wl t rc dk dk# indicates a break in time scale note: 1. di a = data-in for bank a ; di b = data-in for bank b. 576mb: x18, x36 rldram 3 multiplexed address mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 98
figure 65: write-to-read with multiplexed addressing command nop read nop nop nop address ax nop ck ck# t0 t1 t2 t3 t4 t5 t6 t6n t7n t7 t8n t8 dm dont care transitioning data wl qvld dk# dk qk# qk nop nop bank bank a bank b write rl dq di a do b ax ay ay indicates a break in time scale note: 1. di a = data-in for bank a ; di b = data-in for bank b. figure 66: consecutive read bursts with multiplexed addressing command read nop read nop read nop address ax ay bank a ck ck# qk qk# bank qvld dq rl do a t0 t1 t2 t3 read t4 t5 t6 t5n t6n dont care transitioning data bank b bank c bank d ax ax ax ay ay indicates a break in time scale note: 1. do a = data-out for bank a. 576mb: x18, x36 rldram 3 multiplexed addr ess mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 99
figure 67: read-to-write with multiplexed addressing ck ck# command address bank qvld dq read t0 t1 t2 dont care transitioning data write nop t3 t4 t5 t7n nop nop t6 t6n nop wl t7 t8 t9 t9n nop nop dk dk# qk dm qk# do an di bn ax ay ay bank a ax bank b nop nop indicates a break in time scale rl nop note: 1. do a = data-out for bank a; di b = data-in for bank b. 576mb: x18, x36 rldram 3 multiplexed address mode integrated silicon solution, inc. ? www.issi.com 01/17/2012 100
mirror function the mirror function ball (mf) is a dc input used to create mirror ed ballouts for simple dual-loaded clamshell mounting. i f the mf ball is tied low, the address and command balls are in their true layout. if the mf ball is tied high, the address and command balls are mirrored around the central y-axis (column 7). the following table shows the ball assignments when the mf ball is tied high for a x18 device. compare that table to ta- ble 1 (page 12) to see how the address and command balls are mirrored. the same balls are mirrored on the x36 device. table 41: 32 meg x 18 ball assignments with mf ball tied high 1 2 3 4 5 6 7 8 9 10 11 12 13 a v ss v dd nf v ddq nf v ref dq7 v ddq dq8 v dd v ss reset# b v ext v ss nf v ssq nf v ddq dm0 v ddq dq5 v ssq dq6 v ss v ext c v dd nf v ddq nf v ssq nf dk0# dq2 v ssq dq3 v ddq dq4 v dd d a13 v ssq nf v ddq nf v ssq dk0 v ssq qk0 v ddq dq0 v ssq a11 e v ss cs# v ssq nf v ddq nf mf qk0# v ddq dq1 v ssq a0 v ss f a9 a5 v dd a4 a3 ref# zq we# a1 a2 v dd nc 1 a7 g v ss a18 a8 v ss ba0 v ss ck# v ss ba1 v ss a6 a15 v ss h a10 v dd a12 a17 v dd ba2 ck ba3 v dd a16 a14 v dd a19 j v ddq nf v ssq nf v ddq nf v ss qk1# v ddq dq9 v ssq qvld v ddq k nf v ssq nf v ddq nf v ssq dk1 v ssq qk1 v ddq dq10 v ssq dq11 l v dd nf v ddq nf v ssq nf dk1# dq12 v ssq dq13 v ddq dq14 v dd m v ext v ss nf v ssq nf v ddq dm1 v ddq dq15 v ssq dq16 v ss v ext n v ss tck v dd tdo v ddq nf v ref dq17 v ddq tdi v dd tms v ss reset operation the reset signal (reset#) is an asynchronous signal that triggers any time it drops l o w. there are no restrictions for when it can go low. after reset# goes low, it must remain low for 100ns. during this time, the outputs are disabled, odt (r tt ) turns off (high-z), and the dram resets itself. prior to reset# going high, at least 100 stable ck cycles with nop commands must be given to the rldram. after reset# goes high, the dram must be reinitialized as though a normal power-up was executed. all refresh counters on the dram are reset, and data stored in the dram is assumed unknown af- ter reset# has gone low. 576mb: x18, x36 rldram 3 mirror function integrated silicon solution, inc. ? www.issi.com 01/17/2012 101
ieee 1149.1 serial boundary scan (jtag) the rldram 3 device incorporates a serial boundary -scan test access por t (tap) for the purpose of testing the connectivity of the device after it has been mounted on a printed circuit board (pcb). as the complexity of pcb high-density surface mounting techniques increases, the boundary-scan architecture is a valuable resource for inter- connectivity debug. this port operates in accordance with ieee standard 1149.1-2001 (jtag) with the exception of the zq pin. to ensure proper boundary-scan testing of the zq pin, mr1[7] needs to be set to 0 until the jtag testing of the pin is complete. note that upon power up, the default state of the mrs bit m1[7] is low. the jtag test access port utilizes the tap controller on the device, from which the in- struction register, boundary-scan register, bypass register, and id register can be selec- ted. each of these functions of the tap controller is described in detail below. disabling the jtag feature it is possible to operate an rldram 3 device without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v ddq through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state, which will not interfere with the op- eration of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. all the states in figure 68 (page 104) are entered through the serial input of the tms ball. a 0 in the diagram represents a low on the tms ball during the rising edge of tck, while a 1 represents a high on tms. test data-in (tdi) the tdi ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for informa- tion on loading the instruction register, see figure 68 (page 104). tdi is connected to the most significant bit (msb) of any register (see figure 69 (page 104)). test data-out (tdo) the tdo output ball is used to serially clock test instructions and data out from the reg- isters. the tdo output driver is only active during the shift-ir and shift-dr tap con- troller states. in all other states, the tdo ball is in a high-z state. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any regis- ter (see figure 69 (page 104)). 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jtag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 102
tap controller the tap controller is a finite state machine that uses the state of the tms ball at the r ising edge of tck to navigate through its various modes of operation (see figure 68 (page 104)). each state is described in detail below. test-logic-reset the test-logic-reset controller state is entered when tms is held high for at least five consecutive rising edges of tck. as long as tms remains high, the tap controller will remain in the test-logic-reset state. the test logic is inactive during this state. run-test/idle the run-test/idle is a controller state in between scan operations. this state can be maintained by holding tms low. from there, either the data register scan, or subse- quently, the instruction register scan, can be selected. select-dr-scan select-dr-scan is a temporary controller state. all test data registers retain their previ- ous state while here. capture-dr the capture-dr state is where the data is parallel-loaded into the test data registers. if the boundary-scan register is the currently selected register, then the data currently on the balls is latched into the test data registers. shift-dr data is shifted serially through the data register while in this state. as new data is input through the tdi ball, data is shifted out of the tdo ball. exit1-dr, pause-dr, and exit2-dr the purpose of exit1-dr is used to provide a path to return back to the run-test/idle state (through the update-dr state). the pause-dr state is entered when the shifting of data through the test registers needs to be suspended. when shifting is to reconvene, the controller enters the exit2-dr state and then can re-enter the shift-dr state. update-dr when the extest instruction is selected, there are latched parallel outputs of the boun- dary-scan shift register that only change state during the update-dr controller state. instruction register states the instruction register states of the tap controller are similar to the data register states. the desired instruction is serially shifted into the instruction register during the shift-ir state and is loaded during the update-ir state. 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jt ag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 103
figure 68: tap controller state diagram capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 test-logic reset run-test/ idle select ir-scan select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr figure 69: tap controller functional block diagram 0 0 1 2 3 4 5 6 7 0 1 2 29 30 31 . . . 0 1 2 . . . . . tck tms selection circuitry selection circuitry tdo tdi boundry scan register identification register instruction register tap controller bypass register x 1 note: 1. x = 121 for all configurations. 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jtag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 104
performing a tap reset a reset is performed b y for cing tms high (v ddq ) for five rising edges of t ck. this re- set does not affect the operation of the device and may be performed while the device is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. if jtag inputs cannot be guaranteed to be stable during power-up it is recommended that tms be held high for at least 5 consecutive tck cycles prior to boundary scan testing. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the rldram 3 device test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register eight-bit instructions can be serially loaded into the instruction register. this register is loaded during the update-ir state of the tap controller. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode in- struction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two lsbs are loaded with a bina- ry 01 pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed be- tween the tdi and tdo balls. this enables data to be shifted through the device with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is exe- cuted. boundary-scan register the boundary-scan register is connected to all the input and bidirectional balls on the device. several balls are also included in the scan register to reserved balls. the device has a 121-bit register. the boundary-scan register is loaded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the order in which the bits are connected is shown in table 48 (page 110). each bit cor- responds to one of the balls on the rldram package. the msb of the register is con- nected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the rldram 3 and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in table 45 (page 109). 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jt ag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 105
tap instruction set overview there ar e 2 8 differ ent instructions possible with the 8-bit instruction register. all combi- nations used are listed in table 47 (page 110). these six instructions are described in detail below. the remaining instructions are reserved and should not be used. the tap controller used in this rldram 3 device is fully compliant to the ieee 1149.1 convention. instructions are loaded into the tap controller during the shift-ir state when the in- struction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction enables circuitry external to the component package to be tes- ted. boundary-scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary-scan register using the pre- load instruction. thus, during the update-ir state of extest, the output driver is turned on, and the preload data is driven onto the output balls. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the in- struction register. it also places the instruction register between the tdi and tdo balls and enables the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. high-z the high-z instruction causes the bypass register to be connected between the tdi and tdo. this places all rldram outputs into a high-z state. clamp when the clamp instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary-scan register. sample/preload when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, allows a snapshot to be taken of the states of the component's input and output signals without interfering with the normal opera- tion of the assembled board. the snapshot is taken on the rising edge of tck and is cap- tured in the boundry-scan register. the data can then be viewed by shifting through the component's tdo output. the user must be aware that the tap controller clock can only operate at a frequency up to 50 mhz, while the rldram 3 clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jt ag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 106
no guarantee as to the value that will be captured. repeatable results may not be possi- ble. to ensure that the boundar y -scan register will capture the correct value of a signal, the rldram signal must be stabilized long enough to meet the tap controllers capture setup plus hold time ( t cs plus t ch). the rldram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary-scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary-scan register between the tdi and tdo balls. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary-scan path when multiple de- vices are connected together on a board. reserved for future use the remaining instructions are not implemented but are reserved for future use. do not use these instructions. figure 70: jtag operation - loading instruction code and shifting out data tms tdi tck tdo t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tap controller state test-logic- reset run-test idle capture-ir shift-ir select-dr- scan select-ir- scan ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pause-ir pause-ir shift ir exit 1-ir ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 8-bit instruction code dont care transitioning data tms tdi tck tdo tap controller state t10 t11 t12 t13 t14 t15 t16 t17 t18 exit 2-ir select-dr- scan capture-dr shift-dr shift dr exit1-dr update-dr run-test idle update-ir ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) n-bit register between tdi and tdo t19 run-test idle 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jtag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 107
figure 71: tap timing test clock (tck) test mode select (tms) test data-in (tdi) test data-out (tdo) t1 t2 t3 t4 t5 t6 dont care undefined t thtl t mvth t dvth t thdx t tlox t thmx t tlth t thth t tlov table 42: tap input ac logic levels 0c t c +95c; +1.28v v dd +1.42v, unless otherwise noted description symbol min max units input high (logic 1) voltage v ih v ref + 0.225 - v input low (logic 0) voltage v il - v ref - 0.225 v note: 1. all voltages referenced to v ss (gnd). table 43: tap ac electrical characteristics 0c t c +95c; +1.28v v dd +1.42v description symbol min max units clock clock cycle time t thth 20 ns clock frequency f tf 50 mhz clock high time t thtl 10 ns clock low time t tlth 10 ns tdi/tdo times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 10 ns tdi valid to tck high t dvth 5 ns tck high to tdi invalid t thdx 5 ns setup times tms setup t mvth 5 ns 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jtag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 108
table 43: tap ac electrical characteristics (continued) 0c t c +95c; +1.28v v dd +1.42v description symbol min max units capture setup t cs 5 ns hold times tms hold t thmx 5 ns capture hold t ch 5 ns note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary-scan register . t able 44: t ap dc electrical characteristics and operating conditions 0c t c +95c; +1.28v v dd +1.42v, unless otherwise noted description condition symbol min max units notes input high (logic 1) volt- age v ih v ref + 0.15 v ddq v 1, 2 input low (logic 0) voltage v il v ssq v ref - 0.15 v 1, 2 input leakage current 0v v in v dd i li -5.0 5.0 a output leakage current output disabled, 0v v in v ddq i lo -5.0 5.0 a output low voltage i olc = 100a v ol1 0.2 v 1 output low voltage i ol t = 2ma v ol2 0.4 v 1 output high voltage |i ohc | = 100a v oh1 v ddq - 0.2 v 1 output high vol t age |i oht | = 2ma v oh2 v ddq - 0.4 v 1 notes: 1. all voltages referenced to v ss (gnd). 2. see ac overshoot/undershoot specifications section for overshoot and undershoot lim- its. t able 45: identification register definitions 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jtag) instruction field all devices description revision number (31:28) abcd ab = 00 for die revision a cd = 00 for x18, 01 for x36 device id (27:12) 000 1101 0101 00jkidef10100111 def = 000 for 576mb, 001 for 1gb double die package, 010 for 1gb monolithic i = 0 for common i/o jk = 10 for rldram 3 issi jedec id code (11:1) enables unique identification of rldram vendor id register presence indicator (0) 1 indicates the presence of an id register integrated silicon solution, inc. ? www.issi.com 01/17/2012 109
table 46: scan register sizes register name bit size instruction 8 bypass 1 id 32 boundary scan 121 table 47: instruction codes instruction code description extest 0000 0000 captures i/o ring contents; places the boundary-scan register between tdi and tdo; this operation does not af fect rldram 3 operations. id code 0010 0001 loads the id register with the vendor id code and places the register between tdi and tdo; this operation does not af fect rldram 3 operations. sample/preload 0000 0101 captures i/o ring contents; places the boundary-scan register between tdi and tdo. clamp 0000 0111 selects the bypass register to be connected between tdi and tdo; data driven by output balls are determined from values held in the boundary-scan register . high-z 0000 0011 selects the bypass register to be connected between tdi and tdo; all outputs are forced into high-z. bypass 1111 1111 places the bypass register between tdi and tdo; this operation does not affect rldram operations. table 48: boundary scan (exit) bit# ball bit# ball bit# ball 1 n8 42 l7 83 m3 2 n8 43 k7 84 m3 3 m11 44 h1 85 m5 4 m11 45 h4 86 m5 5 m9 46 g2 87 l2 6 m9 47 g3 88 l2 7 l12 48 f1 89 l4 8 l12 49 f5 90 l4 9 l10 50 f4 91 l6 10 l10 51 f2 92 l6 11 l8 52 d1 93 k1 12 l8 53 f7 94 k1 13 k13 54 d7 95 k3 14 k13 55 c7 96 k3 15 k11 56 a13 97 j4 16 k11 57 b7 98 j4 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jtag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 110
table 48: boundary scan (exit) (continued) bit# ball bit# ball bit# ball 17 j10 58 e7 99 j6 18 j10 59 d13 100 k5 19 j8 60 f12 101 j2 20 k9 61 f10 102 a4 21 j12 62 f9 103 a4 22 a10 63 e2 104 a6 23 a10 64 e12 105 a6 24 a8 65 f6 106 b3 25 a8 66 f8 107 b3 26 b11 67 g7 108 b5 27 b11 68 h7 109 b5 28 b9 69 g5 110 c2 29 b9 70 g9 111 c2 30 c12 71 h6 112 c4 31 c12 72 h8 113 c4 32 c10 73 f13 114 c6 33 c10 74 g11 115 c6 34 c8 75 g12 116 e4 35 c8 76 h10 117 e4 36 e10 77 h3 118 d3 37 e10 78 h11 119 d3 38 d11 79 h13 120 e6 39 d11 80 m7 121 d5 40 e8 81 n6 - - 41 d9 82 n6 - - 576mb: x18, x36 rldram 3 ieee 1149.1 serial boundary scan (jtag) integrated silicon solution, inc. ? www.issi.com 01/17/2012 111
576mb: x18, x36 rldram3 ordering information table 49: ordering information commercial range: t c = 0 to +95c frequency speed (tck) trc(min) order part no. organization package 1066 mhz 0.93ns 8ns is49rl18320-093ebl 32m x 18 168 fbga, lead-free IS49RL36160-093ebl 16m x 36 168 fbga, lead-free 10ns is49rl18320-093bl 32m x 18 168 fbga, lead-free IS49RL36160-093bl 16m x 36 168 fbga, lead-free 933 mhz 1.07ns 8ns is49rl18320-107ebl 32m x 18 168 fbga, lead-free IS49RL36160-107ebl 16m x 36 168 fbga, lead-free 10ns is49rl18320-107bl 32m x 18 168 fbga, lead-free IS49RL36160-107bl 16m x 36 168 fbga, lead-free 800 mhz 1.25ns 10ns is49rl18320-125ebl 32m x 18 168 fbga, lead-free IS49RL36160-125ebl 16m x 36 168 fbga, lead-free 12ns is49rl18320-125bl 32m x 18 168 fbga, lead-free IS49RL36160-125bl 16m x 36 168 fbga, lead-free industrial range: t c = -40 to +95c frequency speed (tck) trc(min) order part no. organization package 1066 mhz 0.93ns 8ns is49rl18320-093ebli 32m x 18 168 fbga, lead-free IS49RL36160-093ebli 16m x 36 168 fbga, lead-free 10ns is49rl18320-093bli 32m x 18 168 fbga, lead-free IS49RL36160-093bli 16m x 36 168 fbga, lead-free 933 mhz 1.07ns 8ns is49rl18320-107ebli 32m x 18 168 fbga, lead-free IS49RL36160-107ebli 16m x 36 168 fbga, lead-free 10ns is49rl18320-107bli 32m x 18 168 fbga, lead-free IS49RL36160-107bli 16m x 36 168 fbga, lead-free 800 mhz 1.25ns 10ns is49rl18320-125ebli 32m x 18 168 fbga, lead-free IS49RL36160-125ebli 16m x 36 168 fbga, lead-free 12ns is49rl18320-125bli 32m x 18 168 fbga, lead-free IS49RL36160-125bli 16m x 36 168 fbga, lead-free integrated silicon solution, inc. ? www.issi.com 01/17/2012 112
revision history rev. b, advance ? 10/11 ? changed tqkqx,min to tqkqx,max in figure 52 read data valid window ? added vext information to note 1 of input/output capacitance table ? added table 38 trc_mrs values ? updated tis/tih(base) values on page 50 to 85,120,170 & 65,100, 120 ? corrected error in high-z description. replaced "boundry-scan" with "bypass" ? added verbage in sample/preload description, specifying which edge of tck is used to capture the states of the pins. ? changed jtag boundary scan order. now l7=bit 42, k7=bit 43, j6=bit 99, k5=bit 100 ? updated figure 70 "jtag operation" to match actual operation of the device. ? changed qkx, qkx# to dkx, dkx# in table 33 & 34 derating values for tds/tdh. ? changed cjtag min from 2.0 to 1.5. ? corrected typo in x36 functional block diagram. changed dq1/dk1# to dk1/dk1#. ? added reset# and mf pin ci max spec into input/output capacitance table 6. ? listed qvld with the qk/qk# signals in table 6. ? changed tds base value from 15 to -15 in table 33. ? corrected errors in vseh min, vsel max and vildiff(ac) max definitions. ? updated speed bin table 26 to fill in tck gaps by adjusting tckmin values for -107e, rl=5, -125, rl=6,9,14,15. ? updated table 38 trc_mrs values to reflect the speed bin table changes ? changed the cimax (cmd, addr) spec from 2.1 to 2.25 ? changed the cjtag max from 5.3 to 4.5 ? added x18 & x36 idd values. ? updated tckqk ac timing specifications. ? added in the thermal impedance values rev. a, advance ? 6/11 ? initial release 576mb: x18, x36 rldram 3 revision history integrated silicon solution, inc. ? www.issi.com 01/17/2012 113

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